Xianhua Liu

Orcid: 0000-0003-4777-3847

Affiliations:
  • Peking University, Beijing, China


According to our database1, Xianhua Liu authored at least 16 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2023
High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2020
FTCLNet: Convolutional LSTM with Fourier Transform for Vulnerability Detection.
Proceedings of the 19th IEEE International Conference on Trust, 2020

Efficient arithmetic expression optimization with weighted adjoint matrix.
Proceedings of the 39th IEEE International Performance Computing and Communications Conference, 2020

An Efficient Register Renaming Technique with Delayed Allocation and Register Packing.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2017
Content Look-Aside Buffer for Redundancy-Free Virtual Disk I/O and Caching.
Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

2016
MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
An Energy-Efficient Branch Prediction with Grouped Global History.
Proceedings of the 44th International Conference on Parallel Processing, 2015

Exploration of the Relationship Between Just-in-Time Compilation Policy and Number of Cores.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2012
CVP: an energy-efficient indirect branch prediction with compiler-guided value pattern.
Proceedings of the International Conference on Supercomputing, 2012

Energy-efficient branch prediction with Compiler-guided History Stack.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2010
Research Progress of UniCore CPUs and PKUnity SoCs.
J. Comput. Sci. Technol., 2010

Bit-level optimization for high-level synthesis and FPGA-based acceleration.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2007
Efficient code size reduction without performance loss.
Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

NISD: A Framework for Automatic Narrow Instruction Set Design.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007


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