Xinnan Lin

According to our database1, Xinnan Lin authored at least 13 papers between 2009 and 2023.

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Bibliography

2023
Adaptive receptive field U-shaped temporal convolutional network for vulgar action segmentation.
Neural Comput. Appl., May, 2023

H-MIS: A Hierarchical Multi-Identifier System Based on Blockchain.
Proceedings of the IEEE International Conference on Big Data, 2023

2021
Fine-grained pornographic image recognition with multiple feature fusion transfer learning.
Int. J. Mach. Learn. Cybern., 2021

2020
A SPICE Model of Phase Change Memory for Neuromorphic Circuits.
IEEE Access, 2020

2016
A snake addressing scheme for phase change memory testing.
Sci. China Inf. Sci., 2016

2015
A three-dimensional numerical simulator of phase-change memory by random nucleation and growth approach.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Three-dimensional ovonic threshold switching model with combination of in-band and trap-to-band hopping mechanism for chalcogenide-based phase-change memory.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Investigation of nitrogen enhanced NBTI effect using the universal prediction model.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
An improved SPICE model of phase-change memory (PCM) for peripheral circuits simulation and design.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2011
A new nonlinear parameterized model order reduction technique combining the interpolation method and Proper Orthogonal Decomposition.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Charge-based model for symmetric double-gate MOSFETs with inclusion of channel doping effect.
Microelectron. Reliab., 2010

Asymmetric issues of FinFET device after hot carrier injection and impact on digital and analog circuits.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009


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