Chung-Len Lee

According to our database, Chung-Len Lee authored at least 65 papers between 1990 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

A snake addressing scheme for phase change memory testing.

Xiaole Cui, Zuolin Cheng, Chung-Len Lee, Xinnan Lin, Yiqun Wei, Xiaogang Chen, Zhitang Song

Sci. China Inf. Sci., 2016

2015

Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure.

Zuolin Cheng, Xiaole Cui, Xiaoxin Cui, Chung Len Lee

IET Comput. Digit. Tech., 2015

2013

A UWB mixer with a balanced wide band active balun using crossing centertaped inductor.

Xiangrong Zhang, Xiaole Cui, Bo Wang, Chung Len Lee

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique.

Xuan Yang, Xiaole Cui, Chao Wang, Chung Len Lee

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications.

Zhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung Len Lee

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Enhanced error correction against multiple-bit-upset based on BCH code for SRAM.

Weijia Ma, Xiaole Cui, Chung Len Lee

Proceedings of the IEEE 10th International Conference on ASIC, 2013

New DfT architectures for 3D-SICs with a wireless test port.

Yibo He, Xiaole Cui, Chung Len Lee, Xiaoxin Cui, Yufeng Jin

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A novel test scheme for NAND flash memory based on built-in oscillator ring.

Si Chen, Xiaole Cui, Chung Len Lee

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

Modeling and testing of interference faults in the nano NAND Flash memory.

Jin Zha, Xiaole Cui, Chung Len Lee

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2009

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

IEEE Trans. Very Large Scale Integr. Syst., 2009

2008

Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer.

Weibo Hu, Chung Len Lee, Xin'an Wang

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.

Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu

IEEE Trans. Very Large Scale Integr. Syst., 2007

Multilevel Full-Chip Routing With Testability and Yield Enhancement.

Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

J. Electron. Test., 2007

2006

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.

Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A Scan Matrix Design for Low Power Scan-Based Test.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Finite State Machine Synthesis for At-Speed Oscillation Testability.

Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Oscillation ring based interconnect test scheme for SOC.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC.

Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits.

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen

J. Inf. Sci. Eng., 2003

2002

A low-power high-speed class-AB buffer amplifier for flat-panel-display application.

Chih-Wen Lu, Chung-Len Lee

IEEE Trans. Very Large Scale Integr. Syst., 2002

Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing.

Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen

J. Electron. Test., 2002

Structural Fault Based Specification Reduction for Testing Analog Circuits.

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen

J. Electron. Test., 2002

A Low Power High Speed Class-B Buffer Amplifier for Flat Panel Display Application.

Chih-Wen Lu, Chung-Len Lee

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits.

Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen

Proceedings of the 2002 Design, 2002

A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal.

Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Fault Diagnosis for Linear Analog Circuits.

Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen

J. Electron. Test., 2001

A computer aided engineering system for memory BIST.

Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee

Proceedings of ASP-DAC 2001, 2001

2000

A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier.

Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su

J. Inf. Sci. Eng., 2000

Oscillation Ring Delay Test for High Performance Microprocessors.

Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir

J. Electron. Test., 2000

All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses.

Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee

Proceedings of the 2000 Design, 2000

Is IDDQ testing not applicable for deep submicron VLSI in year 2011?

Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A methodology for fault model development for hierarchical linear systems.

Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model.

Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen

J. Inf. Sci. Eng., 1999

A DFT for semi-DC fault diagnosis for switched-capacitor circuits.

Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang, Jwu E. Chen

Proceedings of the 4th European Test Workshop, 1999

Analog Metrology and Stimulus Selection in a Noisy Environment.

Chauchin Su, Yue-Tsang Chen, Chung-Len Lee

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

A Two-Phase Fault Simulation Scheme for Sequential Circuits.

Wen Ching Wu, Chung-Len Lee, Jwu E. Chen

J. Inf. Sci. Eng., 1998

Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation.

Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Maximization of power dissipation under random excitation for burn-in testing.

Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Identifying invalid states for sequential circuit test generation.

Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Functional test pattern generation for CMOS operational amplifier.

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Fault diagnosis of odd-even sorting networks.

Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines.

Chung-Len Lee, Meng-Lieh Sheu

IEEE Trans. Computers, 1996

Invalid State Identification for Sequential Circuit Test Generation.

Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Universal test set generation for CMOS circuits.

Beyin Chen, Chung-Len Lee

J. Electron. Test., 1995

Identifying Untestable Faults in Sequential Circuits.

Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen

IEEE Des. Test Comput., 1995

Factorization of Multi-Valued Logic Functions.

Hui Min Wang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Identification of robust untestable path delay faults.

Wen Ching Wu, Chung-Len Lee, Jwu E. Chen

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

A programmable multiple-sequence generator for BIST applications.

Meng-Lieh Sheu, Chung-Len Lee

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Fanout fault analysis for digital logic circuits.

Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

A complement-based fast algorithm to generate universal test sets for multi-output functions.

Beyin Chen, Chung-Len Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Simplifying Sequential Circuit Test Generation.

Meng-Lieh Sheu, Chung-Len Lee

IEEE Des. Test Comput., 1994

Complete Test Set for Multiple-Valued Logic Networks.

Hui Min Wang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits.

Hui Min Wang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning.

Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator.

Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1992

MT-SIM a mixed-level transition fault simulator based on parallel patterns.

Chung Len Lee, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang

J. Electron. Test., 1992

Fault Analysis on Two-Level (K+1)-Valued Logic Circuits.

Hui Min Wang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence.

Ching Ping Wu, Chung Len Lee, Wen-Zen Shen

Proceedings of the conference on European design automation, 1992

1991

Single-fault fault-collapsing analysis in sequential logic circuits.

Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Checkpoints in irredundant two-level combinational circuits.

Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen

J. Electron. Test., 1991

1990

A Parallel Pattern Mixed-Level Fault Simulator.

Tyh-Song Hwang, Chung Len Lee, Wen-Zen Shen, Ching Ping Wu

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990