Xiaoqiang Zhang

Orcid: 0000-0002-0167-6374

Affiliations:

Nanjing University, School of Electronic Science and Engineering, Nanjing, China
Anhui Polytechnic University, College of Electrical Engineering, Wuhu, China
Nanjing University of Aeronautics and Astronautics, College of Electrical and Information Engineering, Nanjing, China

According to our database¹, Xiaoqiang Zhang authored at least 18 papers between 2014 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2022

Low delay AES S-box designs based on matrix merging method.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

2021

A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

2020

A low critical path delay structure for composite field AES S-box based on constant matrices multiplication merging.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2020

A full matrix joint optimization method for hardware implementation of AES MixColumns/InvMixColumns.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2020

2019

A new method for resisting collision attack based on parallel random delay S-box.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

Poet: A Power Efficient Hybrid Optical NoC Topology for Heterogeneous CPU-GPU Systems.

[BibT_eX]

[DOI]

Proceedings of the IECON 2019, 2019

2018

An Optimized Design for Compact Masked AES S-Box Based on Composite Field and Common Subexpression Elimination Algorithm.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2018

Compact Hardware Implementations of MISTY1 Block Cipher.

[BibT_eX]

[DOI]

Yasir Khizar

Ning Wu

Xiaoqiang Zhang

J. Circuits Syst. Comput., 2018

High performance AES-GCM implementation based on efficient AES and FR-KOA multiplier.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

Research on physical unclonable functions circuit based on three dimensional integrated circuit.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

2017

FPGA based highly efficient MISTY1 architecture.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A new compact hardware architecture of S-Box for block ciphers AES and SM4.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

2016

Optimization of Area and Delay for Implementation of the Composite Field Advanced Encryption Standard S-Box.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

Against fault attacks based on random infection mechanism.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

Low-delay parallel Chien search architecture for RS decoder.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

2015

High-performance adaptive hybrid wireless NoC architecture based on improved congestion measurement.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

An evolutionary algorithm based on novel hybrid repair strategy for combinational logic circuits.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

2014

An optimized delay-aware common subexpression elimination algorithm for hardware implementation of binary-field linear transform.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Xiaoqiang Zhang

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