Xinyu Shen

Orcid: 0000-0001-5862-376X

According to our database1, Xinyu Shen authored at least 19 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A Protein Structure Prediction Approach Leveraging Transformer and CNN Integration.
CoRR, 2024

Construction and application of artificial intelligence crowdsourcing map based on multi-track GPS data.
CoRR, 2024

DeepGI: An Automated Approach for Gastrointestinal Tract Segmentation in MRI Scans.
CoRR, 2024

2023
The Absence of a Weak-Tie Effect When Predicting Large-Weight Links in Complex Networks.
Entropy, March, 2023

Fragility Induced by Interdependency of Complex Networks and Their Higher-Order Networks.
Entropy, January, 2023

A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A 0.0035-mm<sup>2</sup> 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance Gain.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
A 0.006-mm<sup>2</sup>6-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

A 0.004-mm<sup>2</sup> O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
User-Centered Interference Coordination in the Ultra-Dense Network: a Cluster and Priority Perspective.
Mob. Networks Appl., 2021

Pattern Mining and Detection of Malicious SQL Queries on Anonymization Mechanism.
IEEE Access, 2021

2020
Characterizing Datasets for Social Visual Question Answering, and the New TinySocial Dataset.
Proceedings of the Joint IEEE 10th International Conference on Development and Learning and Epigenetic Robotics, 2020

2018
Quantitative Determining of Ultra-Trace Aluminum Ion in Environmental Samples by Liquid Phase Microextraction Assisted Anodic Stripping Voltammetry.
Sensors, 2018

2016
Saliency detection using secondary quantization in DCT domain.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2016

2009
Research on Energy-Aware Routing Protocol Based on Min Cost Max Flow Algorithm for Mobile Ad Hoc Networks.
Proceedings of the 2009 Second International Symposium on Computational Intelligence and Design, 2009


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