Yang Lv

Orcid: 0000-0001-9062-309X

Affiliations:

University of Minnesota, Department of Electrical and Computer Engineering, Minneapolis, MN, USA

According to our database¹, Yang Lv authored at least 8 papers between 2018 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2026

CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation.

[BibT_eX]

[DOI]

Sohan Salahuddin Mugdho

Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

2025

The Case for Secure Miniservers Beyond the Edge.

[BibT_eX]

[DOI]

IEEE Trans. Computers, October, 2025

2024

On Error Correction for Nonvolatile Processing-In-Memory.

[BibT_eX]

[DOI]

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

On Gate Flip Errors in Computing-In-Memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Experimental demonstration of magnetic tunnel junction-based computational random-access memory.

[BibT_eX]

[DOI]

CoRR, 2023

2022

Error Detection and Correction for Processing in Memory (PiM).

[BibT_eX]

[DOI]

CoRR, 2022

2019

Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions.

[BibT_eX]

[DOI]

Yang Lv

Robert P. Bloom

Jianping Wang

CoRR, 2019

2018

Efficient In-Memory Processing Using Spintronics.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Yang Lv

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