Jonathan D. Harms

According to our database, Jonathan D. Harms authored at least 3 papers between 2010 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Efficient In-Memory Processing Using Spintronics.

Zamshed I. Chowdhury, Jonathan D. Harms, S. Karen Khatamifard, Masoud Zabihi, Yang Lv, Andrew Lyle, Sachin S. Sapatnekar, Ulya R. Karpuzcu, Jianping Wang

IEEE Comput. Archit. Lett., 2018

2013

A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory.

Ki Chul Chun, Hui Zhao, Jonathan D. Harms, Tony Tae-Hyoung Kim, Jianping Wang, Chris H. Kim

IEEE J. Solid State Circuits, 2013

2010

Spintronic logic gates for spintronic data using magnetic tunnel junctions.

Shruti Patil, Andrew Lyle, Jonathan D. Harms, David J. Lilja, Jianping Wang

Proceedings of the 28th International Conference on Computer Design, 2010