Yang Xie

Orcid: 0000-0001-6127-3908

Affiliations:
  • Facebook
  • University of Maryland, College Park, MD, USA (PhD 2018)


According to our database1, Yang Xie authored at least 18 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
Robust and Attack Resilient Logic Locking with a High Application-Level Impact.
ACM J. Emerg. Technol. Comput. Syst., 2021

2020
Keynote: A Disquisition on Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Strong Anti-SAT: Secure and Effective Logic Locking.
IACR Cryptol. ePrint Arch., 2020

2019
Anti-SAT: Mitigating SAT Attack on Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
Circuit Design Obfuscation for Hardware Security.
PhD thesis, 2018

A Combined Optimization-Theoretic and Side- Channel Approach for Attacking Strong Physical Unclonable Functions.
IEEE Trans. Very Large Scale Integr. Syst., 2018

GPU obfuscation: attack and defense strategies.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Security-Aware 2.5D Integrated Circuit Design Flow Against Hardware IP Piracy.
Computer, 2017

Introducing TFUE: The trusted foundry and untrusted employee model in IC supply chain security.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Neural Trojans.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Template Attack Based Deobfuscation of Integrated Circuits.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Security and Vulnerability Implications of 3D ICs.
IEEE Trans. Multi Scale Comput. Syst., 2016

Mitigating SAT Attack on Logic Locking.
IACR Cryptol. ePrint Arch., 2016

2.5D/3D Integration Technologies for Circuit Obfuscation.
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

An optimization-theoretic approach for attacking physical unclonable functions.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
A security-aware design scheme for better hardware Trojan detection sensitivity.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Security-Aware Design Flow for 2.5D IC Technology.
Proceedings of the 5th International Workshop on Trustworthy Embedded Devices, 2015


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