Nithyashankari Gummidipoondi Jayasankaran

Orcid: 0000-0002-5225-7903

According to our database1, Nithyashankari Gummidipoondi Jayasankaran authored at least 7 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES.
CoRR, 2023

2022
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction.
IEEE Trans. Emerg. Top. Comput., 2022

2021
Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
Breaking Analog Locking Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Keynote: A Disquisition on Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits.
Proceedings of the IEEE International Test Conference, 2020

2019
Breaking Analog Locking Techniques via Satisfiability Modulo Theories.
Proceedings of the IEEE International Test Conference, 2019


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