Yang Zhang
Orcid: 0009-0005-1455-5749Affiliations:
- Southeast University, Nanjing, China
According to our database1,
Yang Zhang
authored at least 11 papers
between 2014 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2025
KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2025
A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
Layer-Wise Mixed-Modes CNN Processing Architecture With Double-Stationary Dataflow and Dimension-Reshape Strategy.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024
FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
Proceedings of the International Conference on Compilers, 2023
2018
Proceedings of the 24th International Conference on Pattern Recognition, 2018
2017
An artificial neural network model of LRU-cache misses on out-of-order embedded processors.
Microprocess. Microsystems, 2017
2014
A method for estimating the 3D rendering performance of the SoC in the early design stage.
IEICE Electron. Express, 2014
Hierarchical Pipeline Optimization of Coarse Grained Reconfigurable Processor for Multimedia Applications.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014