Ming Ling

According to our database1, Ming Ling authored at least 28 papers between 2012 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2020
TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Fast modeling L2 cache reuse distance histograms using combined locality information from software traces.
J. Syst. Archit., 2020

AMPS: Accelerating McPAT Power Evaluation Without Cycle-Accurate Simulations.
IEEE Embed. Syst. Lett., 2020

Analytical Modeling the Multi-Core Shared Cache Behavior with Considerations of Data-Sharing and Coherence.
CoRR, 2020

Mapping-Based Dosage of Gait Modification Selection for Multi-Parameter, Subject-Specific Gait Retraining.
IEEE Access, 2020

VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models.
IEEE Access, 2020

Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

TYMER: A Yield-based Performance Model for Timing-speculation SRAM.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Cross-Layer Power and Timing Evaluation Method for Wide Voltage Scaling.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
An Active Mobile Charging and Data Collection Scheme for Clustered Sensor Networks.
IEEE Trans. Veh. Technol., 2019

An embedded implementation of CNN-based hand detection and orientation estimation algorithm.
Mach. Vis. Appl., 2019

Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations.
Microprocess. Microsystems, 2019

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM.
IEEE Access, 2019

Accelerating the Analytical Modeling of Memory Level Parallelism by the Probability Analysis.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

Does the ISA Really Matter? A Simulation Based Investigation.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.
Proceedings of the International Symposium on Memory Systems, 2019

Fast Modeling of the L2 Cache Reuse Distance Histograms from Software Traces.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

A Data-Sharing Aware and Scalable Cache Miss Rates Model for Multi-Core Processors with Multi-Level Cache Hierarchies.
Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems, 2019

A Fast Reduction Method for Path Process Variations Without Time-Consuming Training.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics.
ACM Trans. Embed. Comput. Syst., 2018

Detecting the phase behavior on cache performance using the reuse distance vectors.
J. Syst. Archit., 2018

2017
An artificial neural network model of LRU-cache misses on out-of-order embedded processors.
Microprocess. Microsystems, 2017

Using the first-level cache stack distance histograms to predict multi-level LRU cache misses.
Microprocess. Microsystems, 2017

A mechanistic model of memory level parallelism fed with cache miss rates.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

A trace-driven analytical model with less profiling overhead for DRAM access latencies.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

AFEC: An analytical framework for evaluating cache performance in out-of-order processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2013
A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Dynamic Allocation of SPM Based on Time-Slotted Cache Conflict Graph for System Optimization.
IEICE Trans. Inf. Syst., 2012


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