Ming Ling

According to our database, Ming Ling authored at least 28 papers between 2012 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages.

Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang, Longxing Shi

IEEE Trans. Very Large Scale Integr. Syst., 2020

Fast modeling L2 cache reuse distance histograms using combined locality information from software traces.

Ming Ling, Jiancong Ge, Guangmin Wang

J. Syst. Archit., 2020

AMPS: Accelerating McPAT Power Evaluation Without Cycle-Accurate Simulations.

Wenjie Fu, Ming Ling, Wei Wang, Longxing Shi

IEEE Embed. Syst. Lett., 2020

Analytical Modeling the Multi-Core Shared Cache Behavior with Considerations of Data-Sharing and Coherence.

Ming Ling, Guangmin Wang, Jiancong Ge, Xiaoqian Lu

CoRR, 2020

Mapping-Based Dosage of Gait Modification Selection for Multi-Parameter, Subject-Specific Gait Retraining.

Junkai Xu, Fangyuan Cao, Shi Zhan, Ming Ling, Hai Hu, Peter B. Shull

IEEE Access, 2020

VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models.

Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi

IEEE Access, 2020

Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM.

Shan Shen, Tianxiang Shao, Ming Ling, Jun Yang, Longxing Shi

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

TYMER: A Yield-based Performance Model for Timing-speculation SRAM.

Shan Shen, Liang Pang, Tianxiang Shao, Ming Ling, Xiao Shi, Longxing Shi

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Cross-Layer Power and Timing Evaluation Method for Wide Voltage Scaling.

Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

An Active Mobile Charging and Data Collection Scheme for Clustered Sensor Networks.

Kaiyang Liu, Jun Peng, Liang He, Jianping Pan, Shuo Li, Ming Ling, Zhiwu Huang

IEEE Trans. Veh. Technol., 2019

An embedded implementation of CNN-based hand detection and orientation estimation algorithm.

Li Yang, Zhi Qi, Zeheng Liu, Hao Liu, Ming Ling, Longxing Shi, Xinning Liu

Mach. Vis. Appl., 2019

Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations.

Ming Ling, Xiaojing Shang, Kecheng Ji, Longxing Shi

Microprocess. Microsystems, 2019

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM.

Ming Ling, Xiaojing Shang, Shan Shen, Tianxiang Shao, Jun Yang

IEEE Access, 2019

Accelerating the Analytical Modeling of Memory Level Parallelism by the Probability Analysis.

Yunhao Yan, Ming Ling

Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

Does the ISA Really Matter? A Simulation Based Investigation.

Ming Ling, Xin Xu, Yushen Gu, Zhihua Pan

Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.

Xiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang

Proceedings of the International Symposium on Memory Systems, 2019

Fast Modeling of the L2 Cache Reuse Distance Histograms from Software Traces.

Jiancong Ge, Ming Ling

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

A Data-Sharing Aware and Scalable Cache Miss Rates Model for Multi-Core Processors with Multi-Level Cache Hierarchies.

Guangmin Wang, Jiancong Ge, Yunhao Yan, Ming Ling

Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems, 2019

A Fast Reduction Method for Path Process Variations Without Time-Consuming Training.

Wenjie Fu, Yu Zheng, Leilei Jin, Ming Ling

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics.

Kecheng Ji, Ming Ling, Longxing Shi, Jianping Pan

ACM Trans. Embed. Comput. Syst., 2018

Detecting the phase behavior on cache performance using the reuse distance vectors.

Shan Shen, Ming Ling, Yongtao Zhang, Longxing Shi

J. Syst. Archit., 2018

2017

An artificial neural network model of LRU-cache misses on out-of-order embedded processors.

Kecheng Ji, Ming Ling, Yang Zhang, Longxing Shi

Microprocess. Microsystems, 2017

Using the first-level cache stack distance histograms to predict multi-level LRU cache misses.

Kecheng Ji, Ming Ling, Longxing Shi

Microprocess. Microsystems, 2017

A mechanistic model of memory level parallelism fed with cache miss rates.

Qin Wang, Kecheng Ji, Ming Ling, Longxing Shi

Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

A trace-driven analytical model with less profiling overhead for DRAM access latencies.

Fengying Sun, Kecheng Ji, Ming Ling, Longxing Shi

Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

AFEC: An analytical framework for evaluating cache performance in out-of-order processors.

Kecheng Ji, Ming Ling, Qin Wang, Longxing Shi, Jianping Pan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2013

A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph.

Jianping Wu, Ming Ling, Yang Zhang, Chen Mei, Huan Wang

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

Dynamic Allocation of SPM Based on Time-Slotted Cache Conflict Graph for System Optimization.

Jianping Wu, Ming Ling, Yang Zhang, Chen Mei, Huan Wang

IEICE Trans. Inf. Syst., 2012