Ming Ling
Orcid: 0000-0002-8866-7189
According to our database1,
Ming Ling
authored at least 42 papers
between 2012 and 2024.
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Bibliography
2024
An improved point cloud denoising method in adverse weather conditions based on PP-LiteSeg network.
PeerJ Comput. Sci., 2024
2023
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
Vina-GPU 2.0: Further Accelerating AutoDock Vina and Its Derivatives with Graphics Processing Units.
J. Chem. Inf. Model., April, 2023
Effectiveness Analysis of Multiple Initial States Simulated Annealing Algorithm, a Case Study on the Molecular Docking Tool AutoDock Vina.
IEEE ACM Trans. Comput. Biol. Bioinform., 2023
CoRR, 2023
A New Process Framework for Managing the Fuzzy Front End of New Healthcare Device Development.
Proceedings of the Design, User Experience, and Usability, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Quantitative Analysis and Optimization on the Cache Behavior Influenced by Literal Pools.
IEEE Embed. Syst. Lett., 2022
A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model.
CoRR, 2022
2021
A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Dual fluoroscopic imaging and CT-based finite element modelling to estimate forces and stresses of grafts in anatomical single-bundle ACL reconstruction with different femoral tunnels.
Int. J. Comput. Assist. Radiol. Surg., 2021
Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence.
IEEE Access, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Fast modeling L2 cache reuse distance histograms using combined locality information from software traces.
J. Syst. Archit., 2020
IEEE Embed. Syst. Lett., 2020
Mapping-Based Dosage of Gait Modification Selection for Multi-Parameter, Subject-Specific Gait Retraining.
IEEE Access, 2020
VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models.
IEEE Access, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
IEEE Trans. Veh. Technol., 2019
An embedded implementation of CNN-based hand detection and orientation estimation algorithm.
Mach. Vis. Appl., 2019
Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations.
Microprocess. Microsystems, 2019
Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM.
IEEE Access, 2019
Accelerating the Analytical Modeling of Memory Level Parallelism by the Probability Analysis.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019
RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.
Proceedings of the International Symposium on Memory Systems, 2019
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019
A Data-Sharing Aware and Scalable Cache Miss Rates Model for Multi-Core Processors with Multi-Level Cache Hierarchies.
Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics.
ACM Trans. Embed. Comput. Syst., 2018
J. Syst. Archit., 2018
2017
An artificial neural network model of LRU-cache misses on out-of-order embedded processors.
Microprocess. Microsystems, 2017
Using the first-level cache stack distance histograms to predict multi-level LRU cache misses.
Microprocess. Microsystems, 2017
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017
A trace-driven analytical model with less profiling overhead for DRAM access latencies.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017
AFEC: An analytical framework for evaluating cache performance in out-of-order processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2013
A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Dynamic Allocation of SPM Based on Time-Slotted Cache Conflict Graph for System Optimization.
IEICE Trans. Inf. Syst., 2012