Ming Ling

According to our database1, Ming Ling authored at least 15 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


An Active Mobile Charging and Data Collection Scheme for Clustered Sensor Networks.
IEEE Trans. Vehicular Technology, 2019

An embedded implementation of CNN-based hand detection and orientation estimation algorithm.
Mach. Vis. Appl., 2019

Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations.
Microprocessors and Microsystems - Embedded Hardware Design, 2019

Fast Modeling L2 Cache Reuse Distance Histograms Using Combined Locality Information from Software Traces.
CoRR, 2019

TS Cache: A Fast Cache with Timing-speculation Mechanism Under Low Supply Voltages.
CoRR, 2019

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM.
IEEE Access, 2019

RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.
Proceedings of the International Symposium on Memory Systems, 2019

Fast Modeling of the L2 Cache Reuse Distance Histograms from Software Traces.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics.
ACM Trans. Embedded Comput. Syst., 2018

Detecting the phase behavior on cache performance using the reuse distance vectors.
Journal of Systems Architecture - Embedded Systems Design, 2018

An artificial neural network model of LRU-cache misses on out-of-order embedded processors.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Using the first-level cache stack distance histograms to predict multi-level LRU cache misses.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

AFEC: An analytical framework for evaluating cache performance in out-of-order processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Dynamic Allocation of SPM Based on Time-Slotted Cache Conflict Graph for System Optimization.
IEICE Transactions, 2012