Yangdi Lyu

Orcid: 0000-0001-8322-156X

According to our database1, Yangdi Lyu authored at least 38 papers between 2016 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification.
ACM Trans. Design Autom. Electr. Syst., July, 2026

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation.
CoRR, April, 2026

AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning.
CoRR, March, 2026

Fine-Grained Code Analysis for Processor Fuzzing.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

RLConcolic: Enhancing Concolic Testing via Multi-Step Reinforcement Learning.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

FedBit: Accelerating Privacy-Preserving Federated Learning via Bit-Interleaved Packing and Cross-Layer Co-Design.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
LLM-assisted Path Exploration for RTL Verification.
Proceedings of the 7th ACM/IEEE Symposium on Machine Learning for CAD, 2025

Hot-FV: A Semi-Formal Test Generation Framework for RTL Functional Coverage Using Warm Starting States.
Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

BNRV: A Lightweight SIMD Extension for Efficient BitNet Inference on RISC-V CPUs.
Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

COTIA: Concolic Testing with Intelligent Agent.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

MiCo: End-to-End Mixed Precision Neural Network Co-Exploration Framework for Edge AI.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Invited Paper: CURE-Fuzz: Curiosity-Driven Reinforcement Learning for Agile Hardware Testing.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

DuSGAI: A Dual-Side Sparse GEMM Accelerator with Flexible Interconnects.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

CPP-SGS: Cycle-Accurate Power Prediction Framework via SNN and Genetic Signal Selection.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

An Enhanced Data Packing Method for General Matrix Multiplication in Brakerski/Fan-Vercauteren Scheme.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

MACO: A HW-Mapping Co-optimization Framework for DNN Accelerators.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
HF-NTT: Hazard-Free Dataflow Accelerator for Number Theoretic Transform.
CoRR, 2024

APE-FV: Concolic Testing for RTL Functional Verification Using Adaptive Path Exploration.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024

Efficient Microprocessor Design Space Exploration via Space Partitioning.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024

Microprocessor Design Space Exploration via Space Partitioning and Bayesian Optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
STSearch: State Tracing-based Search Heuristics for RTL Validation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
A Survey on Assertion-based Hardware Verification.
ACM Comput. Surv., January, 2022

2021
Directed Test Generation for Activation of Security Assertions in RTL Models.
ACM Trans. Design Autom. Electr. Syst., 2021

MaxSense: Side-channel Sensitivity Maximization for Trojan Detection Using Statistical Test Patterns.
ACM Trans. Design Autom. Electr. Syst., 2021

Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Scalable Concolic Testing of RTL Models.
IEEE Trans. Computers, 2021

2020
Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

System-on-Chip Security Assertions.
CoRR, 2020

Automated Test Generation for Trojan Detection using Delay-based Side Channel Analysis.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Automated Trigger Activation by Repeated Maximal Clique Sampling.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Automated Test Generation for Activation of Assertions in RTL Models.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Directed Test Generation for Validation of Cache Coherence Protocols.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Efficient Test Generation for Trojan Detection using Side Channel Analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Automated Activation of Multiple Targets in RTL Models using Concolic Testing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Real-time Detection and Localization of DoS Attacks in NoC based SoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Survey of Side-Channel Attacks on Caches and Countermeasures.
J. Hardw. Syst. Secur., 2018

2016
A Fast 2-Approximation Algorithm for Guarding Orthogonal Terrains.
Proceedings of the 28th Canadian Conference on Computational Geometry, 2016


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