Yasser Y. Hanafy

According to our database1, Yasser Y. Hanafy authored at least 11 papers between 2006 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Domain-Specific Modeling and Optimization for Graph Processing on FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2018
Exploring FPGA-specific Optimizations for Irregular OpenCL Applications.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

CommAnalyzer: automated estimation of communication cost and scalability on HPC clusters from sequential code.
Proceedings of the 27th International Symposium on High-Performance Parallel and Distributed Computing, 2018

2017
AutoMatch: An automated framework for relative performance estimation and workload distribution on heterogeneous HPC systems.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

2015
High Performance Sparse LU Solver FPGA Accelerator Using a Static Synchronous Data Flow Model.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Parallel circuit simulation using the direct method on a heterogeneous cloud.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2013
NOA'S-Arc: NISC based, optimized array scalable architecture.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2009
Scientific and Engineering Computing Using ATI Stream Technology.
Comput. Sci. Eng., 2009

2008
Massive parallelization of SPICE device model evaluation on GPU-based SIMD architectures.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008

Enhanced mobile node's reachability through anycasting for MIPv6 regional registrations.
Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008

2006
Design methodologies for high-performance noise-tolerant XOR-XNOR circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006


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