Yasuyuki Hashimoto

According to our database, Yasuyuki Hashimoto authored at least 5 papers between 2003 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.

Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada

IEICE Trans. Electron., 2006

2005

An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs.

Toshiro Tsukada, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada, Koichiro Ishibashi

IEEE J. Solid State Circuits, 2005

Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit.

Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hiroyuki Okada

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application].

Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hirovuki Okada

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003

Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technology.

Hiroyuki Okada, Yasuyuki Hashimoto, Kohji Sakata, Toshiro Tsukada, Koichiro Ishibashi

Proceedings of the ESSCIRC 2003, 2003