Yen-Lin Peng

According to our database, Yen-Lin Peng authored at least 4 papers between 2004 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults.

Yen-Lin Peng, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu

IEEE Trans. Very Large Scale Integr. Syst., 2014

2007

BIST-based diagnosis scheme for field programmable gate array interconnect delay faults.

Yen-Lin Peng, Cheng-Wen Wu, Jing-Jia Liou, Chih-Tsun Huang

IET Comput. Digit. Tech., 2007

2005

A BIST Scheme for FPGA Interconnect Delay Faults.

Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2004

An Application-Independent Delay Testing Methodology for Island-Style FPGA.

Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004