Yung-Fa Chou

According to our database1, Yung-Fa Chou authored at least 52 papers between 1994 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Time-to-Digital Converter Compiler for On-Chip Instrumentation.
IEEE Des. Test, 2020

Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method.
Proceedings of the IEEE International Test Conference in Asia, 2020

2018
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction.
Proceedings of the IEEE International Test Conference in Asia, 2018

A channel-sharable built-in self-test scheme for multi-channel DRAMs.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs.
Proceedings of the International Test Conference in Asia, 2017

Resilient Cell-Based Architecture for Time-to-Digital Converter.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

DLL-Assisted Clock Synchronization Method for Multi-Die ICs.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits.
Proceedings of the 2016 IEEE International Test Conference, 2016

A Test Method for Finding Boundary Currents of 1T1R Memristor Memories.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Hierarchical Test Integration Methodology for 3-D ICs.
IEEE Des. Test, 2015

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.
Proceedings of the Symposium on VLSI Circuits, 2015

A hybrid built-in self-test scheme for DRAMs.
Proceedings of the VLSI Design, Automation and Test, 2015

Temperature-aware online testing of power-delivery TSVs.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Enabling inter-die co-optimization in 3-D IC with TSVs.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Worst-case IR-drop monitoring with 1GHz sampling rate.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

An FPGA-based test platform for analyzing data retention time distribution of DRAMs.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration.
J. Electron. Test., 2012

A SAR ADC missing-decision level detection and removal technique.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

3-D centric technology and realization with TSV.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

3D-IC BISR for stacked memories using cross-die spares.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A built-in self-test scheme for 3D RAMs.
Proceedings of the 2012 IEEE International Test Conference, 2012

Small delay testing for TSVs in 3-D ICs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager.
Proceedings of the 16th European Test Symposium, 2011

A self-testing and calibration method for embedded successive approximation register ADC.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Performance Characterization of TSV in 3D IC via Sensitivity Analysis.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

A Test Integration Methodology for 3D Integrated Circuits.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

CAD reference flow for 3D via-last integrated circuits.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2007
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006
SRAM Cell Current in Low Leakage Design.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

2004
SRAM delay fault modeling and test algorithm development.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Fault Pattern Oriented Defect Diagnosis for Memories.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FAME: A Fault-Pattern Based Memory Failure Analysis Framework.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Defect Oriented Fault Analysis for SRAM.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Flash Memory Built-In Self-Test Using March-Like Algorithm.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2000
etection of SRAM cell stability by lowering array supply voltage.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1994
General Modular Multiplication by Block Multiplication and Table Lookup.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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