Chih-Lung Chen

According to our database1, Chih-Lung Chen authored at least 25 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2020
Towards Accurate and Efficient Classification of Power System Contingencies and Cyber-Attacks Using Recurrent Neural Networks.
IEEE Access, 2020

2016
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
A 7.11mJ/Gb/query data-driven machine learning processor (D<sup>2</sup>MLP) for big data analysis and applications.
Proceedings of the Symposium on VLSI Circuits, 2014

Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection.
IEEE Trans. Multim., 2013

Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes.
IEEE Commun. Lett., 2013

An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes.
IEEE Commun. Lett., 2013

Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes.
Proceedings of the International Conference on Wireless Communications and Signal Processing, 2013

2012
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits, 2012

A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder.
IEEE J. Solid State Circuits, 2012

An improved LT encoding scheme with extended chain lengths.
Proceedings of the International Symposium on Information Theory and its Applications, 2012

Stochastic decoding for LDPC convolutional codes.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Non-repetitive encoding with increased degree-1 encoding symbols for LT codes.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2010
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System.
IEEE J. Solid State Circuits, 2010

2009
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 11.5-Gbps LDPC decoder based on CP-PEG code construction.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications.
IEEE J. Solid State Circuits, 2008


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