Yihan Pan

Orcid: 0000-0002-2666-5540

Affiliations:
  • University of Edinburgh, Institute for Integrated Micro and Nano Systems, School of Engineering, UK
  • University of Edinburgh, Centre for Electronics Frontiers, UK (PhD 2024)
  • University of Southampton, Optoelectronics Research Centre, UK (2020-2022)


According to our database1, Yihan Pan authored at least 14 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
Views: A Hardware-friendly Graph Database Model For Storing Semantic Information.
CoRR, August, 2025

OISMA: On-the-fly In-memory Stochastic Multiplication Architecture for Matrix-Multiplication Workloads.
CoRR, August, 2025

L-Sort: On-Chip Spike Sorting With Efficient Median-of-Median Detection and Localization-Based Clustering.
IEEE Open J. Circuits Syst., 2025

2024
An Energy-Efficient Capacitive-RRAM Content Addressable Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

Design of a low-power Digital-to-Pulse Converter (DPC) for in-memory-computing applications.
Microelectron. J., 2024

An Energy-efficient Capacitive-Memristive Content Addressable Memory.
CoRR, 2024

2022
Multi-State Memristors and Their Applications: An Overview.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

A CMOS-based Characterisation Platform for Emerging RRAM Technologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

High-Density Digital RRAM-based Memory with Bit-line Compute Capability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A RRAM-Based Associative Memory Cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Hybrid CMOS/Memristor Circuit Design Methodology.
CoRR, 2020

A Cluster-Based Neuromorphic ISFET Architecture with Integrated Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


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