Yinan Xu

Orcid: 0000-0002-9702-2542

Affiliations:
  • Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China


According to our database1, Yinan Xu authored at least 11 papers between 2021 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
CodeV: Empowering LLMs With HDL Generation Through Multilevel Summarization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

TraceRTL: Agile Performance Evaluation for Microarchitecture Exploration.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

FastDSE: Enabling Efficient CPU Microarchitecture Design Space Exploration with FPGA Acceleration.
Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

2025
XiangShan: An Open Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards.
IEEE Micro, 2025

DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Processor Verification.
Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture, 2025

2024
XiangShan: An Open-Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards.
Proceedings of the 36th IEEE Hot Chips Symposium, 2024

PathFuzz: Broadening Fuzzing Horizons with Footprint Memory for CPUs.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Functional Verification for Agile Processor Development: A Case for Workflow Integration.
J. Comput. Sci. Technol., July, 2023

Toward Developing High-Performance RISC-V Processors Using Agile Methodology.
IEEE Micro, 2023

2022

2021
Omegaflow: a high-performance dependency-based architecture.
Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021


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