Yingchieh Ho

According to our database1, Yingchieh Ho authored at least 25 papers between 2010 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs.
Sensors, 2017

Standby power reduction using dynamic standby control with voltage keeper.
IEICE Electron. Express, 2017

Energy-efficient standby current suppression with bootstrapped power-gating technique.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A Variation-Tolerant Subthreshold to Superthreshold Level Shifter for Heterogeneous Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Fuzzy Scaled Mutation Evolutionary Computation.
Int. J. Fuzzy Syst., 2016

A 0.5V/22 μW low power transceiver IC for use in ESC intra-body communication system.
Proceedings of the International SoC Design Conference, 2016

Design of a micro-electrode cell for programmable lab-on-CMOS platform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications.
IEEE J. Solid State Circuits, 2014

An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip.
IEICE Trans. Inf. Syst., 2014

A low-power analog-to-digital converter with digitalized amplifier for PAM systems.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Optimized Pre-bond Test Methodology for Silicon Interposer Testing.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO.
IEEE J. Solid State Circuits, 2013

Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.
Proceedings of the 22nd Asian Test Symposium, 2013

Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 0.09 µW Low Power Front-End Biopotential Amplifier for Biosignal Recording.
IEEE Trans. Biomed. Circuits Syst., 2012

A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters.
IEEE J. Solid State Circuits, 2012

Cumulative Differential Nonlinearity Testing of ADCs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A 0.2-0.6 V ring oscillator design using bootstrap technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A 5Gb/s pulse signaling interface for low power on-chip data communication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010


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