Katherine Shu-Min Li

Proceedings of the IEEE International Test Conference, 2022

Trojan Insertions of Fully Programmable Valve Arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication.

[BibT_eX]

[DOI]

Proceedings of the IEEE 31st Asian Test Symposium, 2022

Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Modeling Attack Resistant PUFs Based on Adversarial Attack Against Machine Learning.

[BibT_eX]

[DOI]

Yu-Sheng Chen

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs.

[BibT_eX]

[DOI]

Tzu-Heng Chang

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques.

[BibT_eX]

[DOI]

Nova Cheng-Yen Tsai

Leon Chou

Proceedings of the IEEE International Test Conference, 2021

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Integrated Scratch Marker for Wafer Defect Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2021

Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering.

[BibT_eX]

[DOI]

Leon Li-Yang Chen

Proceedings of the 26th IEEE European Test Symposium, 2021

Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Using Tree Structure to Mine High Temporal Fuzzy Utility Itemsets.

[BibT_eX]

[DOI]

Shyue-Liang Leon Wang

Jerry Chun-Wei Lin

IEEE Access, 2020

Innovative Practice on Wafer Test Innovations.

[BibT_eX]

[DOI]

Dyi-Chung Hu

Hirohito Hashimoto

Li-Fong Tseng

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning.

[BibT_eX]

[DOI]

Leon Li-Yang Chen

Proceedings of the IEEE International Test Conference, 2020

Watermarking for Paper-Based Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Feature Selection for Malicious Traffic Detection with Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the International Computer Symposium, 2020

PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques.

[BibT_eX]

[DOI]

Peter Yi-Yu Liao

Leon Chou

Andrew Yi-Ann Huang

Gus Chang-Hung Han

Proceedings of the IEEE European Test Symposium, 2020

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips.

[BibT_eX]

[DOI]

Microelectron. J., 2019

Exploiting distribution of unknown values in test responses to optimize test output compactors.

[BibT_eX]

[DOI]

Kuan-Ting Yeh

Integr., 2019

TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning.

[BibT_eX]

[DOI]

Andrew Yi-Ann Huang

Cheng-Yen Tsai

Proceedings of the IEEE International Test Conference, 2019

Adversarial Attack against Modeling Attack on PUFs.

[BibT_eX]

[DOI]

Yu-Shen Chen

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

SOLAR: Simultaneous optimization of control-layer pins placement and channel routing in flow-based microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on VLSI Design, 2018

[BibT_eX]

[DOI]

Chin-Hung Lien

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Digital Rights Management for Paper-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

2016 IEEE Education Society Awards, 2016 Frontiers in Education Conference Awards, and Selected IEEE Awards.

[BibT_eX]

[DOI]

IEEE Trans. Educ., 2017

Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Design-for-testability for paper-based digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Testing Clock Distribution Networks.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

A Comprehensive Medicine Management System with Multiple Sources in a Nursing Home in Taiwan.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2016

WristEye: Wrist-Wearable Devices and a System for Supporting Elderly Computer Learners.

[BibT_eX]

[DOI]

IEEE Access, 2016

Test and diagnosis of paper-based microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

A real-time mobile emergency assistance system for helping deaf-mute people/elderly singletons.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2016

An efficient fault tolerance path finding algorithm for improving the robustness of multichannel wireless mesh networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2016

An adaptive residential energy management scheme in the smart home.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2016

Design and development of an extensible multi-protocol automotive gateway.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2016

Test generation for combinational hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

A wearable-glasses-based drowsiness-fatigue-detection system for improving road safety.

[BibT_eX]

[DOI]

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

Side-Channel Attack on Flipped Scan Chains.

[BibT_eX]

[DOI]

Ting-Jui Choi

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

An intelligent vehicular telematics platform for vehicle driving safety supporting system.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Connected Vehicles and Expo, 2015

A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Fast and accurate statistical static timing analysis.

[BibT_eX]

[DOI]

Tsung-Huei Tzeng

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Hybrid Multi-functions Digital Public Address System with Earthquake Early Warning.

[BibT_eX]

[DOI]

Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014

Improving Output Compaction Efficiency with High Observability Scan Chains.

[BibT_eX]

[DOI]

Che-Wei Kao

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Optimized Pre-bond Test Methodology for Silicon Interposer Testing.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test.

[BibT_eX]

[DOI]

Yi-Yu Liao

IEEE Trans. Very Large Scale Integr. Syst., 2013

Oscillation and Transition Tests for Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

CusNoC: Fast Full-Chip Custom NoC Generation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning.

[BibT_eX]

[DOI]

Yingchieh Ho

Liang-Bi Chen

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Low-cost testing of TSVs in 3D stacks with pre-bond testable dies.

[BibT_eX]

[DOI]

Yu-Siao Chen

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process.

[BibT_eX]

[DOI]

Yingchieh Ho

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Synthesis of 3D clock tree with pre-bond testability.

[BibT_eX]

[DOI]

Cheng-Hao Lin

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator.

[BibT_eX]

[DOI]

Yingchieh Ho

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs.

[BibT_eX]

[DOI]

Yi-Yu Liao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Low-power delay test architecture for pre-bond test.

[BibT_eX]

[DOI]

Han-Hsuan Hsu

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Intelligent home management in the smart grids.

[BibT_eX]

[DOI]

Meng-Kang Chiang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

De Bruijn graph-based communication modeling for fault tolerance in smart grids.

[BibT_eX]

[DOI]

Bo-Chuan Cheng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip.

[BibT_eX]

[DOI]

Chih-Yun Pai

Liang-Bi Chen

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Synthesizing Multiple Scan Trees to Optimize Test Application Time.

[BibT_eX]

[DOI]

Jr-Yang Huang

IEEE Des. Test Comput., 2011

Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A Unified Interconnects Testing Scheme for 3D Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction Under Output Constraint.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure.

[BibT_eX]

[DOI]

Chih-Yun Pai

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Low Peak Power ATPG for n-Detection Test.

[BibT_eX]

[DOI]

Kuo-Lin Fu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Level Converting Scan Flip-flops.

[BibT_eX]

[DOI]

Ming-Hua Hsieh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint.

[BibT_eX]

[DOI]

Yu-Chen Hung

Jr-Yang Huang

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement.

[BibT_eX]

[DOI]

Yu-Wei Yang

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Layout-aware scan chain reorder for launch-off-shift transition test coverage.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Design and analysis of skewed-distribution scan chain partition for improved test data compression.

[BibT_eX]

[DOI]

Shih-Cheng Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization.

[BibT_eX]

[DOI]

Jr-Yang Huang

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Multilevel Full-Chip Routing With Testability and Yield Enhancement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling.

[BibT_eX]

[DOI]

Yan-Ting Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis.

[BibT_eX]

[DOI]

Xin-Long Li

Proceedings of the 16th Asian Test Symposium, 2007

2006

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage.

[BibT_eX]

[DOI]

Kuo-Lin Peng

Proceedings of the 15th Asian Test Symposium, 2006

2005

Finite State Machine Synthesis for At-Speed Oscillation Testability.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Oscillation ring based interconnect test scheme for SOC.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Noise-aware buffer planning for interconnect-driven floorplanning.

[BibT_eX]

[DOI]