Yipu Zhang

Orcid: 0009-0007-9465-5807

Affiliations:

Hong Kong University of Science and Technology (HKUST), Department of Electronic & Computer Engineering, Hong Kong

According to our database¹, Yipu Zhang authored at least 9 papers between 2024 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

VLA-IAP: Training-Free Visual Token Pruning via Interaction Alignment for Vision-Language-Action Models.

[BibT_eX]

[DOI]

CoRR, March, 2026

VersaQ-3D: A Reconfigurable Accelerator Enabling Feed-Forward and Generalizable 3D Reconstruction via Versatile Quantization.

[BibT_eX]

[DOI]

CoRR, January, 2026

Guiding multimodal LLMs for efficient visual place recognition.

[BibT_eX]

[DOI]

Pattern Recognit. Lett., 2026

DRACO: A Hardware-Efficient Robot Rigid Body Dynamics Accelerator with Precision-Aware Quantization Framework.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantization.

[BibT_eX]

[DOI]

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator.

[BibT_eX]

[DOI]

CoRR, November, 2025

FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 54th International Conference on Parallel Processing, 2025

SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024

Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

Yipu Zhang

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Bibliography

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