Jiang Xu

Orcid: 0000-0001-9089-7752

Affiliations:
  • Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Hong Kong
  • Princeton University, NJ, USA (PhD 2007)


According to our database1, Jiang Xu authored at least 118 papers between 2002 and 2024.

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Bibliography

2024
PC-oriented Prediction-based Runtime Power Management for GPGPU using Knowledge Transfer.
Proceedings of the 36th ACM Symposium on Parallelism in Algorithms and Architectures, 2024

2023
Memory Workload Synthesis Using Generative AI.
Proceedings of the International Symposium on Memory Systems, 2023

FIONA: Photonic-Electronic CoSimulation Framework and Transferable Prototyping for Photonic Accelerator.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

RONet: Scaling GPU System with Silicon Photonic Chiplet.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Smart Knowledge Transfer-based Runtime Power Management.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Fast and Accurate Statistical Simulation of Shared-Memory Applications on Multicore Systems.
IEEE Trans. Parallel Distributed Syst., 2022

HERO: Pbit High-Radix Optical Switch Based on Integrated Silicon Photonics for Data Center.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Improving the thermal reliability of photonic chiplets on multicore processors.
Integr., 2022

Reduce Footprints of Multiport Interferometers by Cosine-Sine-Decomposition Unfolding.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Power Management for Chiplet-Based Multicore Systems Using Deep Reinforcement Learning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Energy-Efficient High-Performance Photonic Backplane Network for Rack-Scale Computing Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Accelerating Cache Coherence in Manycore Processor through Silicon Photonic Chiplet.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Reliability Concern on Photonic Neural Networks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Improve the Stability and Robustness of Power Management through Model-free Deep Reinforcement Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

PHANES: ReRAM-based photonic accelerator for deep neural networks.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Reduce Loss and Crosstalk in Integrated Silicon-Photonic Multistage Switching Fabrics Through Multichip Partition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Simultaneously Tolerate Thermal and Process Variations Through Indirect Feedback Tuning for Silicon Photonic Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Multi-Core Power Management through Deep Reinforcement Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Rejuvenate Post-Moore's Law Computing with Photonics-Electronics Hybrid Systems.
Proceedings of the International Conference on IC Design and Technology, 2021

2020
Multidevice Collaborative Power Management Through Decentralized Knowledge Sharing.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Efficient Optical Power Delivery System for Hybrid Electronic-Photonic Manycore Processors.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Collaborative Power Management Through Knowledge Sharing Among Multiple Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Scalable Low-Power High-Performance Rack-Scale Optical Network.
Proceedings of the 2019 IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, 2019

Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for Datacenters.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Silicon Photonics for Computing Systems.
ACM J. Emerg. Technol. Comput. Syst., 2018

A Comprehensive Electro-Optical Model for Silicon Photonic Switches.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Decentralized Collaborative Power Management through Multi-Device Knowledge Sharing.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Co-manage power delivery and consumption for manycore systems using reinforcement learning.
Proceedings of the International Conference on Computer-Aided Design, 2018

RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Multi-device collaborative management through knowledge sharing.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Thermal-sensitive design and power optimization for a 3D torus-based optical NoC.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

MOCA: an Inter/Intra-Chip Optical Network for Memory.
Proceedings of the 54th Annual Design Automation Conference, 2017

Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Improve Chip Pin Performance Using Optical Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.
ACM J. Emerg. Technol. Comput. Syst., 2016

Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models.
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016

2015
An Inter/Intra-Chip Optical Network for Manycore Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

An Improved Content-Based Music Recommending Method with Weighted Tags.
Proceedings of the MultiMedia Modeling - 21st International Conference, 2015

Memory Access Analysis of Many-core System with Abundant Bandwidth.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Adaptively tolerate power-gating-induced power/ground noise under process variations.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Coherent crosstalk noise analyses in ring-based optical interconnects.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Alleviate chip I/O pin constraints for multicore processors through optical interconnects.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2014

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.
IEEE Trans. Computers, 2014

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor.
ACM J. Emerg. Technol. Comput. Syst., 2014

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.
ACM J. Emerg. Technol. Comput. Syst., 2014

A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip.
IEEE Des. Test, 2014

Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?".
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

CLAP: a crosstalk and loss analysis platform for optical interconnects.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A systematic network-on-chip traffic modeling and generation methodology.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip.
IEEE Trans. Parallel Distributed Syst., 2013

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8).
NII Shonan Meet. Rep., 2013

A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip.
Microprocess. Microsystems, 2013

System-level analysis of mesh-based hybrid optical-electronic network-on-chip.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2012

2011
Power Gating Aware Task Scheduling in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems.
IEEE Trans. Parallel Distributed Syst., 2011

Novel RD-Optimized VBSME With Matching Highly Data Re-Usable Hardware Architecture.
IEEE Trans. Circuits Syst. Video Technol., 2011

Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models.
IEEE Embed. Syst. Lett., 2011

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A NoC Traffic Suite Based on Real Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Sub-pixel downsampling of video with matching highly data re-use hardware architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A new distributed congestion control mechanism for networks on chip.
Telecommun. Syst., 2010

UNION: A unified inter/intra-chip optical network for chip multiprocessors.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

A Hierarchical Hybrid Optical-Electronic Network-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A highly data reusable and standard-compliant motion estimation hardware architecture.
Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010

Crosstalk noise and bit error rate analysis for optical network-on-chip.
Proceedings of the 47th Design Automation Conference, 2010

2009
Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs.
IEEE Micro, 2009

Efficient algorithms for 2D area management and online task placement on runtime reconfigurable FPGAs.
Microprocess. Microsystems, 2009

Efficient Software Synthesis for Dynamic Single Appearance Scheduling of Synchronous Dataflow.
IEEE Embed. Syst. Lett., 2009

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A Novel Multiple Description Video Coding based on H.264/AVC Video Coding Standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2009

An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

A case study of on-chip sensor network in multiprocessor system-on-chip.
Proceedings of the 2009 International Conference on Compilers, 2009

3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC).
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

A novel optical mesh network-on-chip for gigascale systems-on-chip.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2006
A design methodology for application-specific networks-on-chip.
ACM Trans. Embed. Comput. Syst., 2006

2005
A Methodology for Architectural Design of Multimedia Multiprocessor SoCs.
IEEE Des. Test Comput., 2005

A methodology for design, modeling, and analysis of networks-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

H.264 HDTV Decoder Using Application-Specific Networks-On-Chip.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

2004
A Case Study in Networks-on-Chip Design for Embedded Video.
Proceedings of the 2004 Design, 2004

2003
Augmenting Platform-Based Design with Synthesis Tools.
J. Circuits Syst. Comput., 2003

A wave-pipelined on-chip interconnect structure for networks-on-chips.
Proceedings of the 11th Annual IEEE Symposium on High Performance Interconnects, 2003

2002
Wave pipelining for application-specific networks-on-chips.
Proceedings of the International Conference on Compilers, 2002


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