Yong-Xiao Chen

According to our database, Yong-Xiao Chen authored at least 10 papers between 2012 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

Modeling and testing comparison faults of memristive ternary content addressable memories.

Li-Wei Deng, Jin-Fu Li, Yong-Xiao Chen

Proceedings of the 23rd IEEE European Test Symposium, 2018

2017

A built-in self-test scheme for classifying refresh periods of DRAMs.

Chia-Ming Chang, Yong-Xiao Chen, Jin-Fu Li

Proceedings of the 22nd IEEE European Test Symposium, 2017

2016

Fault modeling and testing of resistive nonvolatile-8T SRAMs.

Yu-Ting Li, Yong-Xiao Chen, Jin-Fu Li

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits.

Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou

Proceedings of the 2016 IEEE International Test Conference, 2016

A built-in method for measuring the delay of TSVs in 3D ICs.

Han-Yu Wu, Yong-Xiao Chen, Jin-Fu Li

Proceedings of the 21th IEEE European Test Symposium, 2016

A Test Method for Finding Boundary Currents of 1T1R Memristor Memories.

Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Fault modeling and testing of 1T1R memristor memories.

Yong-Xiao Chen, Jin-Fu Li

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Testing Inter-Word Coupling Faults of Wide I/O DRAMs.

Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Testing of Non-volatile Logic-Based System Chips.

Yong-Xiao Chen, Jin-Fu Li

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2012

Test cost optimization technique for the pre-bond test of 3D ICs.

Yong-Xiao Chen, Yu-Jen Huang, Jin-Fu Li

Proceedings of the 30th IEEE VLSI Test Symposium, 2012