Chih-Sheng Hou

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs.

[BibT_eX]

[DOI]

Ting-Jun Fu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Testing Disturbance Faults in Various NAND Flash Memories.

[BibT_eX]

[DOI]

J. Electron. Test., 2014

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

An FPGA-based test platform for analyzing data retention time distribution of DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012

Disturbance fault testing on various NAND flash memories.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Memory Built-in Self-Repair Planning Framework for RAMs in SoCs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

A Built-in Method to Repair SoC RAMs in Parallel.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2010

Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs.

[BibT_eX]

[DOI]