Che-Wei Chou

According to our database, Che-Wei Chou authored at least 14 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

DeepMachining: Online Prediction of Machining Errors of Lathe Machines.

Xiang-Li Lu, Hwai-Jung Hsu, Che-Wei Chou, H. T. Kung, Chen-Hsin Lee, Sheng-Mao Cheng

CoRR, 2024

2017

An empirical study of bio manufacturing for the scheduling of hepatitis in vitro diagnostic device with constrained process time window.

Hung-Kai Wang, Chen-Fu Chien, Che-Wei Chou

Comput. Ind. Eng., 2017

Autonomous Deployment of UAVs as Access Points to Serve Wireless Terminals.

Che-Wei Chou, Li-Hsing Yen

Proceedings of the 86th IEEE Vehicular Technology Conference, 2017

2016

A Novel Route Selection and Resource Allocation Approach to Improve the Efficiency of Manual Material Handling System in 200-mm Wafer Fabs for Industry 3.5.

Chen-Fu Chien, Che-Wei Chou, Hui-Chun Yu

IEEE Trans Autom. Sci. Eng., 2016

2015

Hierarchical Test Integration Methodology for 3-D ICs.

Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou

IEEE Des. Test, 2015

Testing Inter-Word Coupling Faults of Wide I/O DRAMs.

Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

A Multiobjective Hybrid Genetic Algorithm for TFT-LCD Module Assembly Scheduling.

Che-Wei Chou, Chen-Fu Chien, Mitsuo Gen

IEEE Trans Autom. Sci. Eng., 2014

2013

A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy.

Che-Wei Chou, Yu-Jen Huang, Jin-Fu Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs.

Chi-Chun Yang, Che-Wei Chou, Jin-Fu Li

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Post-bond test techniques for TSVs with crosstalk faults in 3D ICs.

Yu-Jen Huang, Jin-Fu Li, Che-Wei Chou

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A built-in self-test scheme for 3D RAMs.

Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu

Proceedings of the 2012 IEEE International Test Conference, 2012

2010

A low-cost built-in self-test scheme for an array of memories.

Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li

Proceedings of the 15th European Test Symposium, 2010

Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs.

Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

A Test Integration Methodology for 3D Integrated Circuits.

Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu

Proceedings of the 19th IEEE Asian Test Symposium, 2010