Chih-Yen Lo

According to our database1, Chih-Yen Lo authored at least 17 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction.
Proceedings of the IEEE International Test Conference in Asia, 2018

A channel-sharable built-in self-test scheme for multi-channel DRAMs.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs.
Proceedings of the International Test Conference in Asia, 2017

2016
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits.
Proceedings of the 2016 IEEE International Test Conference, 2016

A Test Method for Finding Boundary Currents of 1T1R Memristor Memories.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Hierarchical Test Integration Methodology for 3-D ICs.
IEEE Des. Test, 2015

A hybrid built-in self-test scheme for DRAMs.
Proceedings of the VLSI Design, Automation and Test, 2015

2014
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

An FPGA-based test platform for analyzing data retention time distribution of DRAMs.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012
A built-in self-test scheme for 3D RAMs.
Proceedings of the 2012 IEEE International Test Conference, 2012

2010
SOC Test Architecture and Method for 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009
Test Integration for SOC Supporting Very Low-Cost Testers.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2007
STEAC: A Platform for Automatic SOC Test Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2006
A network security processor design based on an integrated SOC design and test platform.
Proceedings of the 43rd Design Automation Conference, 2006

2004
An SOC Test Integration Platform and Its Industrial Realization.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004


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