Yoshifumi Ikenaga

According to our database, Yoshifumi Ikenaga authored at least 3 papers between 2006 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.

Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno

IEEE J. Solid State Circuits, 2012

2008

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations.

Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara

IEEE J. Solid State Circuits, 2008

2006

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes.

Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara

IEEE J. Solid State Circuits, 2006