Koichi Nose

According to our database, Koichi Nose authored at least 27 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications.

Koichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami, Daichi Hayashi, Teruhito Tanaka, Takao Toi

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2019

A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm².

Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2015

F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels.

Marian Verhelst, Dennis Sylvester, Makoto Takamiya, Mike Clinton, Kathy Wilcox, Koichi Nose

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Session 16 overview: Emerging technologies enabling next-generation systems: Technology directions subcommittee.

Jan Genoe, Koichi Nose

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2012

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.

Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno

IEEE J. Solid State Circuits, 2012

A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme.

Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno

Proceedings of the Symposium on VLSI Circuits, 2012

2010

An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing.

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2010

A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect.

Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

On-Chip Optical Interconnect.

Keishi Ohashi, Kenichi Nishi, Takanori Shimizu, Masafumi Nakada, Junichi Fujikata, Jun Ushida, Sunao Torii, Koichi Nose, Masayuki Mizuno, Hiroaki Yukawa, Masao Kinoshita, Nobuo Suzuki, Akiko Gomyo, Tsutomu Ishi, Daisuke Okamoto, Katsuya Furue, Toshihide Ueno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Jun Akedo

Proc. IEEE, 2009

Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing.

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A 0.016 mm², 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis.

Koichi Nose, Masayuki Mizuno

IEEE J. Solid State Circuits, 2008

LSI On-Chip Optical Interconnection with Si Nano-Photonics.

Junichi Fujikata, Kenichi Nishi, Akiko Gomyo, Jun Ushida, Tsutomu Ishi, Hiroaki Yukawa, Daisuke Okamoto, Masafumi Nakada, Takanori Shimizu, Masao Kinoshita, Koichi Nose, Masayuki Mizuno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Keishi Ohashi

IEICE Trans. Electron., 2008

2007

Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops.

Toru Nakura, Koichi Nose, Masayuki Mizuno

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

LAGS System Using Data/Instruction Grain Power Control.

Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling.

Koichi Nose, Mikihiro Kajita, Masayuki Mizuno

IEEE J. Solid State Circuits, 2006

Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics.

Keishi Ohashi, Junichi Fujikata, Masafumi Nakada, Tsutomu Ishi, Kenichi Nishi, Hirohito Yamada, Muneo Fukaishi, Masayuki Mizuno, Koichi Nose, Ichiro Ogura, Yutaka Urino, Toshio Baba

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling.

Koichi Nose, Mikihiro Kajita, Masayuki Mizuno

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004

Frequency-hopping vernier clock generators for multiple clock domain SoCs.

Hiroshi Kodama, Masayuki Mizuno, Koichi Nose, Akio Tanaka

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002

V_TH-hopping scheme to reduce subthreshold leakage for low-power processors.

Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai

IEEE J. Solid State Circuits, 2002

Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.

Koichi Nose, Takayasu Sakurai

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001

Design methodology and optimization strategy for dual-VTH scheme using commercially available tools.

Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

V_TH-hopping scheme for 82% power saving in low-voltage processors.

Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

Analysis and future trend of short-circuit power.

Koichi Nose, Takayasu Sakurai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current.

Hiroshi Kawaguchi, Koichi Nose, Takayasu Sakurai

IEEE J. Solid State Circuits, 2000

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).

Koichi Nose, Soo-Ik Chae, Takayasu Sakurai

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Optimization of VDD and VTH for low-power and high speed applications.

Koichi Nose, Takayasu Sakurai

Proceedings of ASP-DAC 2000, 2000

1998

Integrated Current Sensing Device for Micro IDDQ Test.

Koichi Nose, Takayasu Sakurai

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998