Koichi Nose

According to our database1, Koichi Nose authored at least 21 papers between 1998 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm<sup>2</sup>.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2015
F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Session 16 overview: Emerging technologies enabling next-generation systems: Technology directions subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2012
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.
IEEE J. Solid State Circuits, 2012

A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme.
Proceedings of the Symposium on VLSI Circuits, 2012

2010
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing.
IEEE J. Solid State Circuits, 2010

A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
On-Chip Optical Interconnect.
Proc. IEEE, 2009

Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A 0.016 mm<sup>2</sup>, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis.
IEEE J. Solid State Circuits, 2008

LSI On-Chip Optical Interconnection with Si Nano-Photonics.
IEICE Trans. Electron., 2008

2007
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

LAGS System Using Data/Instruction Grain Power Control.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004
Frequency-hopping vernier clock generators for multiple clock domain SoCs.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002
Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Analysis and future trend of short-circuit power.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Optimization of VDD and VTH for low-power and high speed applications.
Proceedings of ASP-DAC 2000, 2000

1998
Integrated Current Sensing Device for Micro IDDQ Test.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998


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