Masayuki Mizuno

According to our database1, Masayuki Mizuno authored at least 43 papers between 1996 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
The numerical analysis of mass evacuation in Taipei 101 with control volume model.
Simul. Model. Pract. Theory, 2019

Formal Verifications of Call-by-Need and Call-by-Name Evaluations with Mutual Recursion.
Proceedings of the Programming Languages and Systems - 17th Asian Symposium, 2019

2018
Formal Verification of the Correspondence Between Call-by-Need and Call-by-Name.
Proceedings of the Functional and Logic Programming - 14th International Symposium, 2018

2013
A 5.5Gb/s 5mm contactless interface containing a 50Mb/s bidirectional sub-channel employing common-mode OOK signaling.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique.
IEEE J. Solid State Circuits, 2012

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.
IEEE J. Solid State Circuits, 2012

A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A Duobinary Signaling for Asymmetric Multi-Chip Communication.
IEICE Trans. Electron., 2011

Dicode Partial Response Signaling over Inductively-Coupled Channel.
IEICE Trans. Electron., 2011

A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests.
IEICE Trans. Electron., 2011

2010
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing.
IEEE J. Solid State Circuits, 2010

A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors.
IEEE J. Solid State Circuits, 2010

A 0.2 mm <sup>2</sup> , 27 Mbps 3 mW ADC/FFT-Less FDM BAN Receiver With Energy Exploitation Capability.
IEEE J. Solid State Circuits, 2010

Gate-oxide early-life failure identification using delay shifts.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A 16Gb/s 1<sup>st</sup>-Tap FFE and 3-Tap DFE in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
On-Chip Optical Interconnect.
Proc. IEEE, 2009

A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery.
IEEE J. Solid State Circuits, 2009

Introduction to the Special Issue on the 2008 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2009

Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Basis-motion torque composition approach: generation of feedforward inputs for control of multi-joint robots.
Proceedings of the 2009 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2009

2008
A 0.016 mm<sup>2</sup>, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis.
IEEE J. Solid State Circuits, 2008

LSI On-Chip Optical Interconnection with Si Nano-Photonics.
IEICE Trans. Electron., 2008

2007
Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link.
IEICE Trans. Electron., 2007

Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

LAGS System Using Data/Instruction Grain Power Control.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling.
IEEE J. Solid State Circuits, 2006

Solid-Electrolyte Nanometer Switch.
IEICE Trans. Electron., 2006

Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A 6.7-fF/μm<sup>2</sup> bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL.
IEEE J. Solid State Circuits, 2005

A nonvolatile programmable solid-electrolyte nanometer switch.
IEEE J. Solid State Circuits, 2005

2004
Frequency-hopping vernier clock generators for multiple clock domain SoCs.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer.
IEEE J. Solid State Circuits, 2003

2001
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1999
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller.
IEEE J. Solid State Circuits, 1999

1997
A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking.
IEEE J. Solid State Circuits, 1997

An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1996
Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI.
IEEE J. Solid State Circuits, 1996

A GHz MOS adaptive pipeline technique using MOS current-mode logic.
IEEE J. Solid State Circuits, 1996


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