Yoshihiko Horio

Orcid: 0000-0003-0115-3095

According to our database1, Yoshihiko Horio authored at least 34 papers between 1991 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
An Extended Spatiotemporal Contextual Learning and Memory Network Model for Hardware Implementation.
Proceedings of the International Neural Network Society Workshop on Deep Learning Innovations and Applications, 2023

2022
Secret-Key Exchange Through Synchronization of Randomized Chaotic Oscillators Aided by Logistic Hash Function.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation.
Proceedings of the International Joint Conference on Neural Networks, 2022

2021
A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021

Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021

Implementation of a Chaotic Neural Network Reservoir on a TSV/$\mu\text{Bump}$ Stacked 3D Cyclic Neural Network Integrated Circuit.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021

2019
Short-term Prediction of Hyperchaotic Flow Using Echo State Network.
Proceedings of the International Joint Conference on Neural Networks, 2019

Chaotic Neural Network Reservoir.
Proceedings of the International Joint Conference on Neural Networks, 2019

An Izhikevich Model Neuron MOS Circuit for Low Voltage Operation.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2019: Theoretical Neural Computation, 2019

2017
An Improved Parameter Value Optimization Technique for the Reflectionless Transmission-Line Model of the Cochlea.
J. Robotics Netw. Artif. Life, 2017

2012
Beta encoders: Symbolic Dynamics and Electronic Implementation.
Int. J. Bifurc. Chaos, 2012

2011
Forced chaos generator with switched CMOS active inductance.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A CMOS nonlinear-map circuit array for threshold-coupled chaotic maps using pulse-modulation approach.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Mutual Information Analyses of Chaotic Neurodynamics Driven by Neuron Selection Methods in Synchronous Exponential Chaotic Tabu Search for Quadratic Assignment Problems.
Proceedings of the Neural Information Processing. Theory and Algorithms, 2010

2009
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Multi-hysteresis VCCS and its Application to Multi-scroll Chaotic Oscillators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Adaptive Feedback Control of Chaotic Neurodynamics in Analog Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007
An IC implementation of a hysteresis two-port VCCS chaotic oscillator.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2005
A mixed analog/digital chaotic neuro-computer system for quadratic assignment problems.
Neural Networks, 2005

An asynchronous spiking chaotic neuron integrated circuit.
Neurocomputing, 2005

One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
Switched-Capacitor Large-Scale Chaotic Neuro-Computer Prototype and Chaotic Search Dynamics.
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2004

2003
Neuron-synapse IC chip-set for large-scale chaotic neural networks.
IEEE Trans. Neural Networks, 2003

An integrated multi-scroll circuit with floating-gate MOSFETs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
Influences of anti-aliasing filter on estimation of the largest Lyapunov exponent.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A simulated LC oscillator using multi-input floating-gate MOSFETS.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999
Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
An asynchronous pulse neural network model and its analog IC implementation.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996
Subadaptive piecewise linear quantization for speech signal (64 kbit/s) compression.
IEEE Trans. Speech Audio Process., 1996

1995
Dynamic Associative Memory Using Switched-Capacitor Chaotic Neurons.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Switched-current chaotic neural network with chaotic simulated annealing.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1994
IC Implementation of Switched-Capacitor Chaotic Neuron.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Switched-capacitor Chaotic Neuron for Chaotic Neural Networks.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1991
A simple method for designing a hierarchical structure transversal filter.
Proceedings of the 1991 International Conference on Acoustics, 1991


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