Takafumi Fukushima

According to our database1, Takafumi Fukushima authored at least 50 papers between 2005 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Ultrawide range square wave impedance analysis circuit with ultra-slow ring-oscillator using gate-induced drain-leakage current.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Experimental evaluation of stimulus current generator with Laplacian edge-enhancement for 3-D stacked retinal prosthesis chip.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration.
Micromachines, 2016

Studying just-in-time defect prediction using cross-project models.
Empirical Software Engineering, 2016

Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE filler.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

New concept of TSV formation methodology using Directed Self-Assembly (DSA).
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku University.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
An empirical study of just-in-time defect prediction using cross-project models.
Proceedings of the 11th Working Conference on Mining Software Repositories, 2014

Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

3D memory chip stacking by multi-layer self-assembly technology.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Development of via-last 3D integration technologies using a new temporary adhesive system.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2011
Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration.
Micromachines, 2011

Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

High density Cu-TSVs and reliability issues.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Stacked SOI pixel detector using versatile fine pitch μ-bump technology.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

A very low area ADC for 3-D stacked CMOS image processing system.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

High-bandwidth data transmission of new transceiver module through optical interconnection.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Chip-level TSV integration for rapid prototyping of 3D system LSIs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Temporary bonding strength control for self-assembly-based 3D integration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

A block-parallel signal processing system for CMOS image sensor with three-dimensional structure.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
High-Density Through Silicon Vias for 3-D LSIs.
Proceedings of the IEEE, 2009

Three-dimensional integration technology and integrated systems.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Heterogeneous integration technology for MEMS-LSI multi-chip module.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

A parallel ADC for high-speed CMOS image processing system with 3D structure.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2005
Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005


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