Yoshitaka Tadaki

According to our database, Yoshitaka Tadaki authored at least 5 papers between 1996 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Multiband Imaging CMOS Image Sensor with Multi-Storied Photodiode Structure.

Yoshiaki Takemoto, Mitsuhiro Tsukimura, Hideki Kato, Shunsuke Suzuki, Jun Aoki, Toru Kondo, Haruhisa Saito, Yuichi Gomi, Seisuke Matsuda, Yoshitaka Tadaki

Sensors, 2018

2015

A 3D stacked CMOS image sensor with 16Mpixel global-shutter mode and 2Mpixel 10000fps mode using 4 million interconnections.

Toru Kondo, Yoshiaki Takemoto, Kenji Kobayashi, Mitsuhiro Tsukimura, Naohiro Takazawa, Hideki Kato, Shunsuke Suzuki, Jun Aoki, Haruhisa Saito, Yuichi Gomi, Seisuke Matsuda, Yoshitaka Tadaki

Proceedings of the Symposium on VLSI Circuits, 2015

2013

A rolling-shutter distortion-free 3D stacked image sensor with -160dB parasitic light sensitivity in-pixel storage node.

Jun Aoki, Yoshiaki Takemoto, Kenji Kobayashi, Naofumi Sakaguchi, Mitsuhiro Tsukimura, Naohiro Takazawa, Hideki Kato, Toru Kondo, Haruhisa Saito, Yuichi Gomi, Yoshitaka Tadaki

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2001

A multigigabit DRAM technology with 6F² open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.

Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh

IEEE J. Solid State Circuits, 2001

1996

A 29-ns 64-Mb DRAM with hierarchical array architecture.

Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato

IEEE J. Solid State Circuits, 1996