Riichiro Takemura

According to our database, Riichiro Takemura authored at least 20 papers between 2001 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Spin-transfer torque RAM technology: Review and prospect.

Takayuki Kawahara, Kenchi Ito, Riichiro Takemura, Hideo Ohno

Microelectron. Reliab., 2012

Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device.

Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara

IEICE Trans. Electron., 2012

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays.

Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh

IEICE Trans. Electron., 2012

0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs.

Akira Kotabe, Kiyoo Itoh, Riichiro Takemura

IEICE Trans. Electron., 2012

A Low-<i>V</i>_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing.

Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh

IEICE Trans. Electron., 2012

Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device.

Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs.

Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme.

Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno

IEEE J. Solid State Circuits, 2010

2009

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays.

Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read.

Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno

IEEE J. Solid State Circuits, 2008

2007

Long-Retention-Time, High-Speed DRAM Array with 12-<i>F</i>² Twin Cell for Sub 1-V Operation.

Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara

IEICE Trans. Electron., 2007

2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read.

Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

SPRAM (SPin-transfer torque RAM) design and its impact on digital systems.

Takayuki Kawahara, Riichiro Takemura, Hiromasa Takahashi, Hideo Ohno

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs.

Kiyoo Itoh, Riichiro Takemura

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM.

Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara

IEEE J. Solid State Circuits, 2006

A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-V_<i>T</i> sense amplifiers.

Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router.

Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara

IEEE J. Solid State Circuits, 2005

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup.

Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara

Proceedings of IEEE International Conference on Communications, 2005

Phase change RAM operated with 1.5-V CMOS as low cost embedded memory.

Kenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2001

A multigigabit DRAM technology with 6F² open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.

Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh

IEEE J. Solid State Circuits, 2001