Goro Kitsukawa

According to our database1, Goro Kitsukawa authored at least 2 papers between 1994 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

1996
A 29-ns 64-Mb DRAM with hierarchical array architecture.
IEEE J. Solid State Circuits, 1996

1994
A charge recycle refresh for Gb-scale DRAM's in file applications.
IEEE J. Solid State Circuits, June, 1994


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