Yu Liu

According to our database, Yu Liu authored at least 19 papers between 2015 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Expert Streaming: Accelerating Low-Batch MoE Inference via Multi-chiplet Architecture and Dynamic Expert Trajectory Scheduling.

Songchen Ma, Hongyi Li, Weihao Zhang, Yonghao Tan, Pingcheng Dong, Yu Liu, Lan Liu, Yuzhong Jiao, Xuejiao Liu, Luhong Liang, Kwang-Ting Cheng

CoRR, March, 2026

31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding.

Pingcheng Dong, Yonghao Tan, Xuejiao Liu, Peng Luo, Yu Liu, Di Pang, Songchen Ma, Xijie Huang, Shih-Yang Liu, Dong Zhang, Zhichao Lu, Luhong Liang, Chi-Ying Tsui, Fengbin Tu, Liang Zhao, Kwang-Ting Cheng

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A 5nm 91.43 TOPS/W 4-Chiplet Generalizable-Rendering-Processor with UCIe-Enabled Cross-Die-Cache and Balance-Aware Progressive Multi-Level Sparsity.

Yonghao Tan, Songchen Ma, Pingcheng Dong, Peng Luo, Zhiyuan Lei, Wencai Lu, Guangxi Ying, Manto Yung, Hai Zhao, Lan Liu, Yuzhong Jiao, Xuejiao Liu, Yu Liu, Li Li, Luhong Liang, Mao Liu, Kwang-Ting Cheng

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

SwinSAM: Fine-grained polyp segmentation in colonoscopy images via segment anything model integrated with a Swin Transformer decoder.

Zhoushan Feng, Yuliang Zhang, Yanhong Chen, Yiyu Shi, Yu Liu, Wen Sun, Lili Du, Dunjin Chen

Biomed. Signal Process. Control., 2025

A 28nm 0.22μJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation.

Pingcheng Dong, Yonghao Tan, Xuejiao Liu, Peng Luo, Yu Liu, Luhong Liang, Yitong Zhou, Di Pang, Manto Yung, Dong Zhang, Xijie Huang, Shih-Yang Liu, Yongkun Wu, Fengshi Tian, Chi-Ying Tsui, Fengbin Tu, Kwang-Ting Cheng

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

CoXplorer: Multi-Staged Co-Exploration Framework for AI Model Compression and Accelerator Design.

Songchen Ma, Junyi Wu, Yonghao Tan, Pingcheng Dong, Peng Luo, Di Pang, Yu Liu, Xuejiao Liu, Luhong Liang, Kwang-Ting Cheng, Fengbin Tu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design.

Yonghao Tan, Pingcheng Dong, Yongkun Wu, Yu Liu, Xuejiao Liu, Peng Luo, Shih-Yang Liu, Xijie Huang, Dong Zhang, Luhong Liang, Kwang-Ting Cheng

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection.

Yifan Qin, Zhenge Jia, Zheyu Yan, Jay Mok, Manto Yung, Yu Liu, Xuejiao Liu, Wujie Wen, Luhong Liang, Kwang-Ting (Tim) Cheng, Xiaobo Sharon Hu, Yiyu Shi

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

Genetic Quantization-Aware Approximation for Non-Linear Operations in Transformers.

Pingcheng Dong, Yonghao Tan, Dong Zhang, Tianwei Ni, Xuejiao Liu, Yu Liu, Peng Luo, Luhong Liang, Shih-Yang Liu, Xijie Huang, Huaiyu Zhu, Yun Pan, Fengwei An, Kwang-Ting Cheng

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad.

Xianghong Hu, Xuejiao Liu, Yu Liu, Haowei Zhang, Xijie Huang, Xihao Guan, Luhong Liang, Chi-Ying Tsui, Xiaoming Xiong, Kwang-Ting Cheng

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

2022

ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor With Compiler-Architecture Co-Design.

Jianwei Zheng, Yu Liu, Xuejiao Liu, Luhong Liang, Deming Chen, Kwang-Ting Cheng

IEEE Trans. Computers, 2022

TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network.

Xiaomeng Wang, Xuejiao Liu, Xianghong Hu, Xiaopeng Zhong, Xizi Chen, Yu Liu, Patrick Kong, Fengshi Tian, Chi-Ying Tsui

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2020

Optimize FPGA-Based Neural Network Accelerator with Bit-Shift Quantization.

Yu Liu, Xuejiao Liu, Luhong Liang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018

Software Fault Detection and Correction: Modeling and Applications

Rui Peng, Yan-Fu Li, Yu Liu

Springer Briefs in Computer Science, Springer, ISBN: 978-981-13-1161-1, 2018

2017

A Dynamic-Bayesian-Network-Based Fault Diagnosis Methodology Considering Transient and Intermittent Faults.

Baoping Cai, Yu Liu, Min Xie

IEEE Trans Autom. Sci. Eng., 2017

2016

A multiphase dynamic Bayesian networks methodology for the determination of safety integrity levels.

Baoping Cai, Yu Liu, Qian Fan

Reliab. Eng. Syst. Saf., 2016

Modeling and analysis of reliability of multi-release open source software incorporating both fault detection and correction processes.

Jianfeng Yang, Yu Liu, Min Xie, Ming Zhao

J. Syst. Softw., 2016

2015

A New Framework and Application of Software Reliability Estimation Based on Fault Detection and Correction Processes.

Yu Liu, Min Xie, Jianfeng Yang, Ming Zhao

Proceedings of the 2015 IEEE International Conference on Software Quality, 2015

A reliability analysis framework based on time-varying Dynamic Bayesian Network.

Yu Liu, Baoping Cai

Proceedings of the 2015 IEEE International Conference on Industrial Engineering and Engineering Management, 2015