Yu-Wen Tsay

According to our database, Yu-Wen Tsay authored at least 5 papers between 1993 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1998

Integrating logic retiming and register placement.

Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Preserving HDL synthesis hierarchy for cell placement.

Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin

Proceedings of the 1997 International Symposium on Physical Design, 1997

1995

A row-based cell placement method that utilizes circuit structural properties.

Yu-Wen Tsay, Youn-Long Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Combining technology mapping and placement for delay-minimization in FPGA designs.

Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1993

Combining technology mapping and placement for delay-optimization in FPGA designs.

Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993