Yih-Chih Chou

According to our database1, Yih-Chih Chou authored at least 9 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Clocking for HPC Design: Challenges and Experience Sharing.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2016
Top-level activity-driven clock tree synthesis with clock skew variation considered.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2002
Effective enforcement of path-delay constraints inperformance-driven placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001
A performance-driven standard-cell placer based on a modified force-directed algorithm.
Proceedings of the 2001 International Symposium on Physical Design, 2001

A 3-step approach for performance-driven whole-chip routing.
Proceedings of ASP-DAC 2001, 2001

1998
Integrating logic retiming and register placement.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

A graph-partitioning-based approach for multi-layer constrained via minimization.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998


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