Yuhao Zhang

Orcid: 0000-0002-0118-8135

Affiliations:
  • Tsinghua University, Department of Computer Science and Technology, Beijing, China
  • Shandong University, School of Computer Science and Technology, Qingdao, China (PhD 2022)


According to our database1, Yuhao Zhang authored at least 15 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2025
Achieving Wire-Latency Storage Systems by Exploiting Hardware ACKs.
Proceedings of the 22nd USENIX Symposium on Networked Systems Design and Implementation, 2025

Deft: A Scalable Tree Index for Disaggregated Memory.
Proceedings of the Twentieth European Conference on Computer Systems, 2025

2024
Static Scheduling of Weight Programming for DNN Acceleration with Resource Constrained PIM.
ACM Trans. Embed. Comput. Syst., November, 2024

A Semantic-Integrated LSM-Tree-Based Key-Value Storage Engine for Blockchain Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024

Perseid: A Secondary Indexing Mechanism for LSM-Based Storage Systems.
ACM Trans. Storage, May, 2024

ASHL: An Adaptive Multi-Stage Distributed Deep Learning Training Scheme for Heterogeneous Environments.
IEEE Trans. Computers, January, 2024

Ares-Flash: Efficient Parallel Integer Arithmetic Operations Using NAND Flash Memory.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Towards High-Throughput Neural Network Inference with Computational BRAM on Nonvolatile FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
A Multiagent Reinforcement Learning-Assisted Cache Cleaning Scheme for DM-SMR.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Revisiting Secondary Indexing in LSM-based Storage Systems with Persistent Memory.
Proceedings of the 2023 USENIX Annual Technical Conference, 2023

2022
A Practical Highly Paralleled ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

PQ-PIM: A pruning-quantization joint optimization framework for ReRAM-based processing-in-memory DNN accelerator.
J. Syst. Archit., 2022

2021
An efficient highly parallelized ReRAM-based architecture for motion estimation of HEVC.
J. Syst. Archit., 2021

Accelerating DCNNs via Cooperative Weight/Activation Compression.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2021

2020
PattPIM: A Practical ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020


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