Yukinori Sato

Orcid: 0000-0002-3491-1692

According to our database1, Yukinori Sato authored at least 39 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
A Case for Deploying Dynamic Neural Network on Edge-Cloud Continuum Environment.
Proceedings of the IEEE International Conference on Edge Computing and Communications, 2024

A Microservice Scheduler for Heterogeneous Resources on Edge-Cloud Computing Continuum.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024

2022
Apple Brand Texture Classification Using Neural Network Model.
Proceedings of the Advanced Information Networking and Applications, 2022

Study on Apple Texture Measuring Equipment Manipulated with Hand.
Proceedings of the Advances on P2P, Parallel, Grid, Cloud and Internet Computing, 2022

2021
A simulation of a memory subsystem using a highly energy-efficient but erroneous MRAM.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Thread-Aware Cache Simulator for HPC Application Tuning.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Hodgkin-Huxley-Based Neural Simulation with Networks Connecting to Near-Neighbor Neurons.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
An FPGA Implementation of a Gaussian Process Based Predictor for Sequential Time Series Data.
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

2019
An Autotuning Framework for Scalable Execution of Tiled Code via Iterative Polyhedral Compilation.
ACM Trans. Archit. Code Optim., 2019

Apple Brand Classification Using CNN Aiming at Automatic Apple Texture Estimation.
Proceedings of the Advances on P2P, Parallel, Grid, Cloud and Internet Computing, 2019

2017
Energy-Performance Modeling of Speculative Checkpointing for Exascale Systems.
IEICE Trans. Inf. Syst., 2017

An Accurate Simulator of Cache-Line Conflicts to Exploit the Underlying Cache Performance.
Proceedings of the Euro-Par 2017: Parallel Processing - 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28, 2017

ExanaDBT: A Dynamic Compilation System for Transparent Polyhedral Optimizations at Runtime.
Proceedings of the Computing Frontiers Conference, 2017

2015
Investigating potential performance benefits of memory layout optimization based on roofline model.
Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, 2015

Exana: an execution-driven application analysis tool for assisting productive performance tuning.
Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, 2015

Workshop Preview of the 2nd International Workshop on Software for Parallel Systems (SEPS 2015).
Proceedings of the Companion Proceedings of the 2015 ACM SIGPLAN International Conference on Systems, 2015

2014
Design and implementation of a two-dimensional sound field solver based on the Digital Huygens' Model.
Microprocess. Microsystems, 2014

Identifying Program Loop Nesting Structures during Execution of Machine Code.
IEICE Trans. Inf. Syst., 2014

Fast and Energy-efficient Breadth-First Search on a Single NUMA System.
Proceedings of the Supercomputing - 29th International Conference, 2014

Online Memory Access Pattern Analysis on an Application Profiling Tool.
Proceedings of the Second International Symposium on Computing and Networking, 2014

2013
High and stable performance under adverse traffic patterns of tori-connected torus network.
Comput. Electr. Eng., 2013

2012
Dynamic Communication Performance Enhancement in Hierarchical Torus Network by Selection Algorithm.
J. Networks, 2012

High Performance Hierarchical Torus Network Under Adverse Traffic Patterns.
J. Networks, 2012

Evaluating reconfigurable dataflow computing using the Himeno benchmark.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Design of a FPGA-based Timing Sharing Architecture for Sound Rendering Applications.
Proceedings of the Ninth International Conference on Information Technology: New Generations, 2012

Whole program data dependence profiling to unveil parallel regions in the dynamic execution.
Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012

2011
Improving accuracy of host load predictions on computational grids by artificial neural networks.
Int. J. Parallel Emergent Distributed Syst., 2011

On Nonuniform Traffic Pattern of Modified Hierarchical 3D-Torus Network.
IEICE Trans. Inf. Syst., 2011

A Prediction-Based Green Scheduler for Datacenters in Clouds.
IEICE Trans. Inf. Syst., 2011

Decentralized task-oriented local group generation for robot swarms.
Proceedings of the 8th International Conference on Ubiquitous Robots and Ambient Intelligence, 2011

On-the-fly detection of precise loop nests across procedures on a dynamic binary translation system.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
Performance evaluation of a Green Scheduling Algorithm for energy savings in Cloud computing.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Dynamic Communication Performance of a Modified Hierarchical 3D-Torus Network under Non-uniform Traffic Patterns.
Proceedings of the First International Conference on Networking and Computing, 2010

A FPGA implementation of the two-dimensional Digital Huygens' Model.
Proceedings of the International Conference on Field-Programmable Technology, 2010

2009
Dynamic Communication Performance of the TESH Network under Nonuniform Traffic Patterns.
J. Networks, 2009

TTN: A High Performance Hierarchical Interconnection Network for Massively Parallel Computers.
IEICE Trans. Inf. Syst., 2009

2007
Power Estimation of Partitioned Register Files in a Clustered Architecture with Performance Evaluation.
IEICE Trans. Inf. Syst., 2007

2005
Cooperation of Neighboring PEs in Clustered Architectures.
Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005

An Operand Status Based Instruction Steering Scheme for Clustered Architectures.
Proceedings of the 2005 International Conference on Computer Design, 2005


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