Yunjae Suh

According to our database1, Yunjae Suh authored at least 14 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A Low-Power Class-AB Gm-Based Amplifier With Application to an 11-bit Pipelined ADC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC.
J. Circuits Syst. Comput., 2016

2015
Computationally efficient, real-time motion recognition based on bio-inspired visual and cognitive processing.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

2014
A voltage-scalable 10-b pipelined ADC with current-mode amplifier.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS.
IEEE J. Solid State Circuits, 2013

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL.
IEEE J. Solid State Circuits, 2013

2012
A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation.
IEICE Trans. Electron., 2010

A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
Deadzone-Minimized Systematic Offset-Free Phase Detectors.
IEICE Trans. Electron., 2008


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