Seon-Kyoo Lee

According to our database¹, Seon-Kyoo Lee authored at least 20 papers between 2009 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2021

A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

Issues and Key Technologies for Next Generation 3D NAND.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2021

2020

A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2016

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Current-Mode Transceiver for Silicon Interposer Channel.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

2013

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A 95fJ/b current-mode transceiver for 10mm on-chip interconnect.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS.

[BibT_eX]

[DOI]

Young Hun Seo

Seon-Kyoo Lee

Jae-Yoon Sim

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2011

2010

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Seon-Kyoo Lee

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