Yusuke Kanazawa

According to our database1, Yusuke Kanazawa authored at least 10 papers between 2002 and 2009.

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Bibliography

2009
A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS.
IEEE J. Solid State Circuits, 2009

2007
A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model.
Int. J. Unconv. Comput., 2005

2004
A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection.
Int. J. Robotics Autom., 2004

A MOS circuit for bursting neural oscillators with excitable oregonators.
IEICE Electron. Express, 2004

2003
A subthreshold MOS neuron circuit based on the Volterra system.
IEEE Trans. Neural Networks, 2003

Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses.
J. Robotics Mechatronics, 2003

2002
A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology.
Proceedings of the IEEE International Conference on Systems, Man and Cybernetics: Bridging the Digital Divide, Yasmine Hammamet, Tunisia, October 6-9, 2002, 2002


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