Yoshihito Amemiya

According to our database1, Yoshihito Amemiya authored at least 62 papers between 1994 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2011
Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator.
Int. J. Unconv. Comput., 2011

A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
A 1-muhboxW 600- hboxppm/<sup>circ</sup>hboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A CMOS Phase-Shift oscillator Based on the conduction of Heat.
J. Circuits Syst. Comput., 2010

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs.
IEICE Trans. Electron., 2010

High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair.
IEICE Trans. Electron., 2010

A behavioral model of unipolar resistive RAMs and its application to HSPICE integration.
IEICE Electron. Express, 2010

Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits.
Proceedings of the Neural Information Processing. Theory and Algorithms, 2010

2009
A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs.
IEEE J. Solid State Circuits, 2009

Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons.
Proceedings of the International Joint Conference on Neural Networks, 2009

Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits.
Proceedings of the Neural Information Processing, 16th International Conference, 2009

Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
On Digital LSI Circuits Exploiting Collision-Based Fusion Gates.
Int. J. Unconv. Comput., 2008

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs.
IEICE Electron. Express, 2008

Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning.
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008

A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits.
Proceedings of the ESSCIRC 2008, 2008

2007
CMOS Smart Sensor for Monitoring the Quality of Perishables.
IEEE J. Solid State Circuits, 2007

A Single-Electron Reaction-Diffusion Device for Computation of a Voronoi Diagram.
Int. J. Unconv. Comput., 2007

A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters.
Neurocomputing, 2007

A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors.
Int. J. Bifurc. Chaos, 2007

Discrete Dynamical Systems Consisting of Single-electron Circuits.
Int. J. Bifurc. Chaos, 2007

An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning.
Proceedings of the International Joint Conference on Neural Networks, 2007

Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning.
Proceedings of the Neural Information Processing, 14th International Conference, 2007

2006
A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator.
Int. J. Bifurc. Chaos, 2006

A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions.
IEICE Trans. Electron., 2006

Design methodologies for compact logic circuits based on collision-based computing.
IEICE Electron. Express, 2006

Power-supply circuits for ultralow-power subthreshold MOS-LSIs.
IEICE Electron. Express, 2006

2005
Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A quadrilateral-object composer for binary images with reaction-diffusion cellular automata.
Parallel Algorithms Appl., 2005

Reaction-Diffusion Systems Consisting of Single-Electron Oscillators.
Int. J. Unconv. Comput., 2005

Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model.
Int. J. Unconv. Comput., 2005

Ultralow-Power Current Reference Circuit with Low Temperature Dependence.
IEICE Trans. Electron., 2005

On the fault tolerance of a clustered single-electron neural network for differential enhancement.
IEICE Electron. Express, 2005

Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller.
J. Robotics Mechatronics, 2004

A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection.
Int. J. Robotics Autom., 2004

Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata.
IEICE Electron. Express, 2004

A MOS circuit for bursting neural oscillators with excitable oregonators.
IEICE Electron. Express, 2004

Design of an Artificial Central Pattern Generator with Feedback Controller.
Intell. Autom. Soft Comput., 2004

An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion.
IEEE Trans. Neural Networks, 2003

A subthreshold MOS neuron circuit based on the Volterra system.
IEEE Trans. Neural Networks, 2003

Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses.
J. Robotics Mechatronics, 2003

Biomorphic Analog Devices based on Reaction-Diffusion Systems.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

2002
A CMOS Reaction-Diffusion Circuit Based on Cellular-Automaton Processing Emulating the Belousov-Zhabotinsky Reaction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology.
Proceedings of the IEEE International Conference on Systems, Man and Cybernetics: Bridging the Digital Divide, Yasmine Hammamet, Tunisia, October 6-9, 2002, 2002

2000
An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks.
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

1998
nu-MOS cellular-automaton devices for intelligent image sensors.
Proceedings of the Knowledge-Based Intelligent Electronic Systems, 1998

1994
An all-analog expandable neural network LSI with on-chip backpropagation learning.
IEEE J. Solid State Circuits, September, 1994


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