Yusuke Nagasaka

According to our database1, Yusuke Nagasaka authored at least 10 papers between 2014 and 2022.

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Bibliography

2022
A traffic-aware memory-cube network using bypassing.
Microprocess. Microsystems, April, 2022

Efficient Collision-Free MTTKRP Algorithm for Multi-core CPUs with Less Memory Usage.
Proceedings of the 22nd IEEE International Symposium on Cluster, 2022

2021
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

2019
Performance optimization, modeling and analysis of sparse matrix-matrix products on multi-core and many-core processors.
Parallel Comput., 2019

Batched Sparse Matrix Multiplication for Accelerating Graph Convolutional Networks.
Proceedings of the 19th IEEE/ACM International Symposium on Cluster, 2019

2018
MRG8: Random Number Generation for the Exascale Era.
Proceedings of the Platform for Advanced Scientific Computing Conference, 2018

High-Performance Sparse Matrix-Matrix Products on Intel KNL and Multicore Architectures.
Proceedings of the 47th International Conference on Parallel Processing, 2018

2017
High-Performance and Memory-Saving Sparse General Matrix-Matrix Multiplication for NVIDIA Pascal GPU.
Proceedings of the 46th International Conference on Parallel Processing, 2017

2016
Adaptive Multi-level Blocking Optimization for Sparse Matrix Vector Multiplication on GPU.
Proceedings of the International Conference on Computational Science 2016, 2016

2014
Cache-aware sparse matrix formats for Kepler GPU.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014


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