Yoshiya Shikama

According to our database, Yoshiya Shikama authored at least 5 papers between 2021 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2023

A Compression Router for Low-Latency Network-on-Chip.

Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi

IEICE Trans. Inf. Syst., February, 2023

2022

A traffic-aware memory-cube network using bypassing.

Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi

Microprocess. Microsystems, April, 2022

A Hardware Trojan Exploiting Coherence Protocol on NoCs.

Yoshiya Shikama, Michihiro Koibuchi, Hideharu Amano

Proceedings of the Parallel and Distributed Computing, Applications and Technologies, 2022

2021

Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths.

Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi

Proceedings of the 29th Euromicro International Conference on Parallel, 2021

A Case for Low-Latency Network-on-Chip using Compression Routers.

Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi

Proceedings of the 29th Euromicro International Conference on Parallel, 2021