Ryuta Kawano

Orcid: 0000-0001-8918-0674

According to our database1, Ryuta Kawano authored at least 17 papers between 2015 and 2022.

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Bibliography

2022
A traffic-aware memory-cube network using bypassing.
Microprocess. Microsystems, April, 2022

Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks.
Proceedings of the Tenth International Symposium on Computing and Networking, 2022

2021
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph.
Proceedings of the ACIT 2021: The 8th International Virtual Conference on Applied Computing & Information Technology, Kanazawa, Japan, June 20, 2021

2020
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks.
IEICE Trans. Inf. Syst., 2020

A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks.
IEICE Trans. Inf. Syst., 2020

Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks.
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

2019
Deadlock-Free Layered Routing for Infiniband Networks.
Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

2018
k-Optimized Path Routing for High-Throughput Data Center Networks.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

2017
Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator.
IEICE Trans. Inf. Syst., 2017

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing.
IEICE Trans. Inf. Syst., 2017

A Layout-Oriented Routing Method for Low-Latency HPC Networks.
IEICE Trans. Inf. Syst., 2017

HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies.
Proceedings of the 23rd IEEE International Conference on Parallel and Distributed Systems, 2017

2016
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Body bias grain size exploration for a coarse grained reconfigurable accelerator.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free.
Proceedings of the 15th IEEE/ACIS International Conference on Computer and Information Science, 2016

2015
Optimized Core-Links for Low-Latency NoCs.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015


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