Yuta Tsubouchi
Orcid: 0000-0002-6607-573X
According to our database1,
Yuta Tsubouchi
authored at least 9 papers
between 2011 and 2022.
Collaborative distances:
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Bibliography
2022
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.
IEEE J. Solid State Circuits, 2022
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2019
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.
IEEE J. Solid State Circuits, 2019
A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2013
Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication".
IEEE J. Solid State Circuits, 2013
2012
A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication.
IEEE J. Solid State Circuits, 2012
A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011