Takashi Toi

Orcid: 0000-0002-0197-9447

According to our database1, Takashi Toi authored at least 6 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.
IEEE J. Solid State Circuits, 2022

A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2019
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.
IEEE J. Solid State Circuits, 2019

A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2015
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator.
Proceedings of the Nordic Circuits and Systems Conference, 2015


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