Jun Deguchi
Orcid: 0000-0002-3414-5537
According to our database1,
Jun Deguchi
authored at least 35 papers
between 2006 and 2023.
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Bibliography
2023
CoRR, 2023
Can a Frozen Pretrained Language Model be used for Zero-shot Neural Retrieval on Entity-centric Questions?
CoRR, 2023
RaLLe: A Framework for Developing and Evaluating Retrieval-Augmented Large Language Models.
Proceedings of the 2023 Conference on Empirical Methods in Natural Language Processing, 2023
2022
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.
IEEE J. Solid State Circuits, 2022
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2022
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the Computer Vision - ECCV 2022, 2022
2021
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2021
Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2021
IEICE Trans. Electron., 2021
F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Session 15 Overview: Compute-in-Memory Processors for Deep Neural Networks Machine Learning Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
IEICE Trans. Electron., 2020
2019
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.
IEEE J. Solid State Circuits, 2019
A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Post Training Weight Compression with Distribution-based Filter-wise Quantization Step.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019
2018
A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing.
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2014
A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter.
IEICE Trans. Electron., 2012
2010
A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010
A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2006
Measurement of neuromagnetic fields accompanying movements by patient with acute stroke.
Syst. Comput. Jpn., 2006
Proceedings of the 2006 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2006